Ruby: Connect system port in Ruby network test

This patch moves the connection of the system port to create_system in
Ruby.py. Thereby it allows the failing Ruby test (and other Ruby
systems) to run again.

9 files changed, 11 insertions, 15 deletions

diff --git a/configs/example/se.py b/configs/example/se.py
index 572364482..b94652ac0 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -184,7 +184,6 @@ if options.ruby:
     options.use_map = True
     Ruby.create_system(options, system)
     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-    system.system_port = system.ruby._sys_port_proxy.port
 else:
     system.system_port = system.membus.port
     system.physmem.port = system.membus.port
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index b2342eed4..920eac019 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -105,6 +105,10 @@ def create_system(options, system, piobus = None, dma_devices = []):
     # full-fledged controller
     system.sys_port_proxy = sys_port_proxy
 
+    # Connect the system port for loading of binaries etc
+    system.system_port = system.sys_port_proxy.port
+
+
     #
     # Set the network classes based on the command line options
     #
@@ -182,5 +186,4 @@ def create_system(options, system, piobus = None, dma_devices = []):
     ruby.profiler = ruby_profiler
     ruby.mem_size = total_mem_size
     ruby._cpu_ruby_ports = cpu_sequencers
-    ruby._sys_port_proxy = sys_port_proxy
     ruby.random_seed    = options.random_seed
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 2517e7670..49f152017 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -109,10 +109,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
      #
      ruby_port.access_phys_mem = False
 
-
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index b14f0e5b1..6f01167d3 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -46,6 +46,8 @@ for cpu in cpus:
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 07851ae9f..3b6d58b3b 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -43,4 +43,7 @@ system = System(cpu = cpu,
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
+
 root = Root(system = system)
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index a7e598b0a..b63833ccf 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -105,9 +105,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
     #
     ruby_port.access_phys_mem = False
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 705f13ef3..f8a7b1d17 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -47,6 +47,8 @@ for cpu in cpus:
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 58ca862e1..d57ccea15 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -88,9 +88,6 @@ for (i, cpu) in enumerate(system.cpu):
     cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
     cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 359421a49..1d67f6f97 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -85,9 +85,6 @@ assert(len(system.ruby._cpu_ruby_ports) == 1)
 cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
 cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------