SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.

12 files changed, 166 insertions, 222 deletions

diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index e0cbf019d..7e683364a 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -34,40 +34,33 @@ Import('*')
 if env['TARGET_ISA'] == 'alpha':
     Source('ev5.cc')
     Source('faults.cc')
+    Source('freebsd/system.cc')
+    Source('idle_event.cc')
     Source('interrupts.cc')
     Source('ipr.cc')
     Source('isa.cc')
     Source('kernel_stats.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/system.cc')
     Source('osfpal.cc')
     Source('pagetable.cc')
+    Source('process.cc')
     Source('regredir.cc')
     Source('remote_gdb.cc')
     Source('stacktrace.cc')
+    Source('system.cc')
     Source('tlb.cc')
+    Source('tru64/process.cc')
+    Source('tru64/system.cc')
+    Source('tru64/tru64.cc')
     Source('utility.cc')
     Source('vtophys.cc')
 
     SimObject('AlphaInterrupts.py')
+    SimObject('AlphaSystem.py')
     SimObject('AlphaTLB.py')
 
-    if env['FULL_SYSTEM']:
-        SimObject('AlphaSystem.py')
-
-        Source('idle_event.cc')
-        Source('system.cc')
-
-        Source('freebsd/system.cc')
-        Source('linux/system.cc')
-        Source('tru64/system.cc')
-
-    else:
-        Source('process.cc')
-
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
-
-        Source('tru64/tru64.cc')
-        Source('tru64/process.cc')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 2bc913f92..06ba96003 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -44,8 +44,6 @@
 
 namespace AlphaISA {
 
-#if FULL_SYSTEM
-
 ////////////////////////////////////////////////////////////////////////
 //
 //  Machine dependent functions
@@ -76,8 +74,6 @@ zeroRegisters(CPU *cpu)
     cpu->thread->setFloatReg(ZeroReg, 0.0);
 }
 
-#endif
-
 ////////////////////////////////////////////////////////////////////////
 //
 //
@@ -201,10 +197,8 @@ ISA::readIpr(int idx, ThreadContext *tc)
     return retval;
 }
 
-#ifdef DEBUG
 // Cause the simulator to break when changing to the following IPL
 int break_ipl = -1;
-#endif
 
 void
 ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
@@ -264,10 +258,8 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
         // write entire quad w/ no side-effect
         old = ipr[idx];
         ipr[idx] = val;
-#if FULL_SYSTEM
         if (tc->getKernelStats())
             tc->getKernelStats()->context(old, val, tc);
-#endif
         break;
 
       case IPR_DTB_PTE:
@@ -294,14 +286,11 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
-#if FULL_SYSTEM
         if (tc->getKernelStats())
             tc->getKernelStats()->swpipl(ipr[idx]);
-#endif
         break;
 
       case IPR_DTB_CM:
-#if FULL_SYSTEM
         if (val & 0x18) {
             if (tc->getKernelStats())
                 tc->getKernelStats()->mode(Kernel::user, tc);
@@ -309,7 +298,6 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
             if (tc->getKernelStats())
                 tc->getKernelStats()->mode(Kernel::kernel, tc);
         }
-#endif
 
       case IPR_ICM:
         // only write two mode bits - processor mode
@@ -486,8 +474,6 @@ copyIprs(ThreadContext *src, ThreadContext *dest)
 
 } // namespace AlphaISA
 
-#if FULL_SYSTEM
-
 using namespace AlphaISA;
 
 Fault
@@ -537,5 +523,3 @@ SimpleThread::simPalCheck(int palFunc)
 
     return true;
 }
-
-#endif // FULL_SYSTEM
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index c66c6f8ab..a6d3ef2d0 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -35,11 +35,9 @@
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
 #include "mem/page_table.hh"
 #include "sim/process.hh"
-#endif
+#include "sim/full_system.hh"
 
 namespace AlphaISA {
 
@@ -107,12 +105,12 @@ FaultName IntegerOverflowFault::_name = "intover";
 FaultVect IntegerOverflowFault::_vect = 0x0501;
 FaultStat IntegerOverflowFault::_count;
 
-#if FULL_SYSTEM
-
 void
 AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
+    if (!FullSystem)
+        return;
     countStat()++;
 
     PCState pc = tc->pcState();
@@ -135,32 +133,36 @@ void
 ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
+    if (!FullSystem)
+        return;
     panic("Arithmetic traps are unimplemented!");
 }
 
 void
 DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    // Set fault address and flags.  Even though we're modeling an
-    // EV5, we use the EV6 technique of not latching fault registers
-    // on VPTE loads (instead of locking the registers until IPR_VA is
-    // read, like the EV5).  The EV6 approach is cleaner and seems to
-    // work with EV5 PAL code, but not the other way around.
-    if (!tc->misspeculating() &&
-        reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
-        // set VA register with faulting address
-        tc->setMiscRegNoEffect(IPR_VA, vaddr);
-
-        // set MM_STAT register flags
-        MachInst machInst = inst->machInst;
-        tc->setMiscRegNoEffect(IPR_MM_STAT,
-            (((Opcode(machInst) & 0x3f) << 11) |
-             ((Ra(machInst) & 0x1f) << 6) |
-             (flags & 0x3f)));
-
-        // set VA_FORM register with faulting formatted address
-        tc->setMiscRegNoEffect(IPR_VA_FORM,
-            tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+    if (FullSystem) {
+        // Set fault address and flags.  Even though we're modeling an
+        // EV5, we use the EV6 technique of not latching fault registers
+        // on VPTE loads (instead of locking the registers until IPR_VA is
+        // read, like the EV5).  The EV6 approach is cleaner and seems to
+        // work with EV5 PAL code, but not the other way around.
+        if (!tc->misspeculating() &&
+            reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+            // set VA register with faulting address
+            tc->setMiscRegNoEffect(IPR_VA, vaddr);
+
+            // set MM_STAT register flags
+            MachInst machInst = inst->machInst;
+            tc->setMiscRegNoEffect(IPR_MM_STAT,
+                (((Opcode(machInst) & 0x3f) << 11) |
+                 ((Ra(machInst) & 0x1f) << 6) |
+                 (flags & 0x3f)));
+
+            // set VA_FORM register with faulting formatted address
+            tc->setMiscRegNoEffect(IPR_VA_FORM,
+                tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+        }
     }
 
     AlphaFault::invoke(tc);
@@ -169,49 +171,55 @@ DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    if (!tc->misspeculating()) {
-        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
-        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
-            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+    if (FullSystem) {
+        if (!tc->misspeculating()) {
+            tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+            tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+                tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+        }
     }
 
     AlphaFault::invoke(tc);
 }
 
-#else
-
 void
 ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    Process *p = tc->getProcessPtr();
-    TlbEntry entry;
-    bool success = p->pTable->lookup(pc, entry);
-    if (!success) {
-        panic("Tried to execute unmapped address %#x.\n", pc);
+    if (FullSystem) {
+        ItbFault::invoke(tc);
     } else {
-        VAddr vaddr(pc);
-        tc->getITBPtr()->insert(vaddr.page(), entry);
+        Process *p = tc->getProcessPtr();
+        TlbEntry entry;
+        bool success = p->pTable->lookup(pc, entry);
+        if (!success) {
+            panic("Tried to execute unmapped address %#x.\n", pc);
+        } else {
+            VAddr vaddr(pc);
+            tc->getITBPtr()->insert(vaddr.page(), entry);
+        }
     }
 }
 
 void
 NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    Process *p = tc->getProcessPtr();
-    TlbEntry entry;
-    bool success = p->pTable->lookup(vaddr, entry);
-    if (!success) {
-        if (p->fixupStackFault(vaddr))
-            success = p->pTable->lookup(vaddr, entry);
-    }
-    if (!success) {
-        panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
+    if (FullSystem) {
+        DtbFault::invoke(tc, inst);
     } else {
-        tc->getDTBPtr()->insert(vaddr.page(), entry);
+        Process *p = tc->getProcessPtr();
+        TlbEntry entry;
+        bool success = p->pTable->lookup(vaddr, entry);
+        if (!success) {
+            if (p->fixupStackFault(vaddr))
+                success = p->pTable->lookup(vaddr, entry);
+        }
+        if (!success) {
+            panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
+        } else {
+            tc->getDTBPtr()->insert(vaddr.page(), entry);
+        }
     }
 }
 
-#endif
-
 } // namespace AlphaISA
 
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 3da97ccb4..7eddd14eb 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -33,7 +33,6 @@
 #define __ARCH_ALPHA_FAULTS_HH__
 
 #include "arch/alpha/pagetable.hh"
-#include "config/full_system.hh"
 #include "mem/request.hh"
 #include "sim/faults.hh"
 
@@ -49,10 +48,8 @@ class AlphaFault : public FaultBase
     virtual bool skipFaultingInstruction() {return false;}
     virtual bool setRestartAddress() {return true;}
   public:
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
     virtual FaultVect vect() = 0;
     virtual FaultStat & countStat() = 0;
 };
@@ -111,10 +108,8 @@ class ArithmeticFault : public AlphaFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class InterruptFault : public AlphaFault
@@ -147,10 +142,8 @@ class DtbFault : public AlphaFault
     FaultName name() const = 0;
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class NDtbMissFault : public DtbFault
@@ -167,10 +160,8 @@ class NDtbMissFault : public DtbFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class PDtbMissFault : public DtbFault
@@ -247,10 +238,8 @@ class ItbFault : public AlphaFault
     FaultName name() const = 0;
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class ItbPageFault : public ItbFault
@@ -265,10 +254,8 @@ class ItbPageFault : public ItbFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class ItbAcvFault : public ItbFault
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index eecf695da..4bbf83cce 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -821,43 +821,41 @@ decode OPCODE default Unknown::unknown() {
         }
     }
 
-#if FULL_SYSTEM
-    0x00: CallPal::call_pal({{
-        if (!palValid ||
-            (palPriv
-             && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
-            // invalid pal function code, or attempt to do privileged
-            // PAL call in non-kernel mode
-            fault = new UnimplementedOpcodeFault;
-        } else {
-            // check to see if simulator wants to do something special
-            // on this PAL call (including maybe suppress it)
-            bool dopal = xc->simPalCheck(palFunc);
-
-            if (dopal) {
-                xc->setMiscReg(IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+    0x00: decode FullSystem {
+        0: decode PALFUNC {
+            format EmulatedCallPal {
+                0x00: halt ({{
+                    exitSimLoop("halt instruction encountered");
+                }}, IsNonSpeculative);
+                0x83: callsys({{
+                    xc->syscall(R0);
+                }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
+                // Read uniq reg into ABI return value register (r0)
+                0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
+                // Write uniq reg with value from ABI arg register (r16)
+                0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
             }
         }
-    }}, IsNonSpeculative);
-#else
-    0x00: decode PALFUNC {
-        format EmulatedCallPal {
-            0x00: halt ({{
-                exitSimLoop("halt instruction encountered");
-            }}, IsNonSpeculative);
-            0x83: callsys({{
-                xc->syscall(R0);
-            }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
-            // Read uniq reg into ABI return value register (r0)
-            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
-            // Write uniq reg with value from ABI arg register (r16)
-            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
-        }
+        default: CallPal::call_pal({{
+            if (!palValid ||
+                (palPriv
+                 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
+                // invalid pal function code, or attempt to do privileged
+                // PAL call in non-kernel mode
+                fault = new UnimplementedOpcodeFault;
+            } else {
+                // check to see if simulator wants to do something special
+                // on this PAL call (including maybe suppress it)
+                bool dopal = xc->simPalCheck(palFunc);
+
+                if (dopal) {
+                    xc->setMiscReg(IPR_EXC_ADDR, NPC);
+                    NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+                }
+            }
+        }}, IsNonSpeculative);
     }
-#endif
 
-#if FULL_SYSTEM
     0x1b: decode PALMODE {
         0: OpcdecFault::hw_st_quad();
         1: decode HW_LDST_QUAD {
@@ -924,8 +922,6 @@ decode OPCODE default Unknown::unknown() {
         }
     }
 
-#endif
-
     format BasicOperate {
         // M5 special opcodes use the reserved 0x01 opcode space
         0x01: decode M5FUNC {
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index a8788051f..a08cddaec 100644
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -34,7 +34,7 @@
 #include "arch/alpha/types.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
+#include "sim/full_system.hh"
 
 class ThreadContext;
 
@@ -83,9 +83,8 @@ class Predecoder
     {
         ext_inst = inst;
         emiIsReady = true;
-#if FULL_SYSTEM
-        ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
-#endif
+        if (FullSystem)
+            ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
     }
 
     bool
diff --git a/src/arch/alpha/regredir.cc b/src/arch/alpha/regredir.cc
index 991138f11..861ded4d1 100644
--- a/src/arch/alpha/regredir.cc
+++ b/src/arch/alpha/regredir.cc
@@ -31,22 +31,13 @@
  */
 
 #include "arch/alpha/regredir.hh"
-#include "config/full_system.hh"
 
 namespace AlphaISA {
 
-#if FULL_SYSTEM
 const int reg_redir[NumIntRegs] = {
     /*  0 */ 0, 1, 2, 3, 4, 5, 6, 7,
     /*  8 */ 32, 33, 34, 35, 36, 37, 38, 15,
     /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
     /* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
-#else
-const int reg_redir[NumIntRegs] = {
-    /*  0 */ 0, 1, 2, 3, 4, 5, 6, 7,
-    /*  8 */ 8, 9, 10, 11, 12, 13, 14, 15,
-    /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
-    /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
-#endif
 
 } // namespace AlphaISA
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index 88d453754..4b285e7ec 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -121,15 +121,12 @@
 
 #include <string>
 
-#include "config/full_system.hh"
-#if FULL_SYSTEM
-#include "arch/alpha/vtophys.hh"
-#endif
 
 #include "arch/alpha/kgdb.h"
 #include "arch/alpha/regredir.hh"
 #include "arch/alpha/remote_gdb.hh"
 #include "arch/alpha/utility.hh"
+#include "arch/alpha/vtophys.hh"
 #include "base/intmath.hh"
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"
@@ -142,6 +139,7 @@
 #include "mem/physical.hh"
 #include "mem/port.hh"
 #include "sim/system.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 using namespace AlphaISA;
@@ -158,51 +156,51 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
 bool
 RemoteGDB::acc(Addr va, size_t len)
 {
-#if !FULL_SYSTEM
-    panic("acc function needs to be rewritten for SE mode\n");
-#else
-    Addr last_va;
-
-    va = TruncPage(va);
-    last_va = RoundPage(va + len);
-
-    do  {
-        if (IsK0Seg(va)) {
-            if (va < (K0SegBase + pmem->size())) {
-                DPRINTF(GDBAcc, "acc:   Mapping is valid  K0SEG <= "
-                        "%#x < K0SEG + size\n", va);
+    if (FullSystem) {
+        Addr last_va;
+
+        va = TruncPage(va);
+        last_va = RoundPage(va + len);
+
+        do  {
+            if (IsK0Seg(va)) {
+                if (va < (K0SegBase + pmem->size())) {
+                    DPRINTF(GDBAcc, "acc:   Mapping is valid  K0SEG <= "
+                            "%#x < K0SEG + size\n", va);
+                    return true;
+                } else {
+                    DPRINTF(GDBAcc, "acc:   Mapping invalid %#x "
+                            "> K0SEG + size\n", va);
+                    return false;
+                }
+            }
+
+            /**
+             * This code says that all accesses to palcode (instruction
+             * and data) are valid since there isn't a va->pa mapping
+             * because palcode is accessed physically. At some point this
+             * should probably be cleaned up but there is no easy way to
+             * do it.
+             */
+
+            if (PcPAL(va) || va < 0x10000)
                 return true;
-            } else {
-                DPRINTF(GDBAcc, "acc:   Mapping invalid %#x > K0SEG + size\n",
-                        va);
+
+            Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
+            PageTableEntry pte =
+                kernel_pte_lookup(context->getPhysPort(), ptbr, va);
+            if (!pte.valid()) {
+                DPRINTF(GDBAcc, "acc:   %#x pte is invalid\n", va);
                 return false;
             }
-        }
-
-        /**
-         * This code says that all accesses to palcode (instruction
-         * and data) are valid since there isn't a va->pa mapping
-         * because palcode is accessed physically. At some point this
-         * should probably be cleaned up but there is no easy way to
-         * do it.
-         */
-
-        if (PcPAL(va) || va < 0x10000)
-            return true;
-
-        Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
-        PageTableEntry pte =
-            kernel_pte_lookup(context->getPhysPort(), ptbr, va);
-        if (!pte.valid()) {
-            DPRINTF(GDBAcc, "acc:   %#x pte is invalid\n", va);
-            return false;
-        }
-        va += PageBytes;
-    } while (va < last_va);
+            va += PageBytes;
+        } while (va < last_va);
 
-    DPRINTF(GDBAcc, "acc:   %#x mapping is valid\n", va);
-    return true;
-#endif
+        DPRINTF(GDBAcc, "acc:   %#x mapping is valid\n", va);
+        return true;
+    } else {
+        panic("acc function needs to be rewritten for SE mode\n");
+    }
 }
 
 /*
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 5d40f85d7..0048e43e9 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -30,35 +30,33 @@
  */
 
 #include "arch/alpha/utility.hh"
-
-#if FULL_SYSTEM
 #include "arch/alpha/vtophys.hh"
 #include "mem/vport.hh"
-#endif
+#include "sim/full_system.hh"
 
 namespace AlphaISA {
 
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-#if FULL_SYSTEM
-    const int NumArgumentRegs = 6;
-    if (number < NumArgumentRegs) {
-        if (fp)
-            return tc->readFloatRegBits(16 + number);
-        else
-            return tc->readIntReg(16 + number);
+    if (FullSystem) {
+        const int NumArgumentRegs = 6;
+        if (number < NumArgumentRegs) {
+            if (fp)
+                return tc->readFloatRegBits(16 + number);
+            else
+                return tc->readIntReg(16 + number);
+        } else {
+            Addr sp = tc->readIntReg(StackPointerReg);
+            VirtualPort *vp = tc->getVirtPort();
+            uint64_t arg = vp->read<uint64_t>(sp +
+                               (number-NumArgumentRegs) * sizeof(uint64_t));
+            return arg;
+        }
     } else {
-        Addr sp = tc->readIntReg(StackPointerReg);
-        VirtualPort *vp = tc->getVirtPort();
-        uint64_t arg = vp->read<uint64_t>(sp +
-                           (number-NumArgumentRegs) * sizeof(uint64_t));
-        return arg;
+        panic("getArgument() is Full system only\n");
+        M5_DUMMY_RETURN;
     }
-#else
-    panic("getArgument() is Full system only\n");
-    M5_DUMMY_RETURN;
-#endif
 }
 
 void
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index c0c985c34..a9b5c4cba 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -36,7 +36,6 @@
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
 #include "base/misc.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "arch/alpha/ev5.hh"
@@ -96,9 +95,7 @@ RoundPage(Addr addr)
 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
 
 void initIPRs(ThreadContext *tc, int cpuId);
-#if FULL_SYSTEM
 void initCPU(ThreadContext *tc, int cpuId);
-#endif
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d0e15eee9..e4940a55f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -412,7 +412,7 @@ BaseSimpleCPU::postExecute()
 
     TheISA::PCState pc = tc->pcState();
     Addr instAddr = pc.instAddr();
-    if (thread->profile) {
+    if (FullSystem && thread->profile) {
         bool usermode = TheISA::inUserMode(tc);
         thread->profilePC = usermode ? 1 : instAddr;
         ProfileNode *node = thread->profile->consume(tc, curStaticInst);
@@ -466,7 +466,8 @@ BaseSimpleCPU::postExecute()
     }
     /* End power model statistics */
 
-    traceFunctions(instAddr);
+    if (FullSystem)
+        traceFunctions(instAddr);
 
     if (traceData) {
         traceData->dump();
diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index 09cbb166d..6d79b3fec 100644
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -36,12 +36,6 @@
 #include "kern/operatingsystem.hh"
 #include "sim/byteswap.hh"
 
-#if FULL_SYSTEM
-
-class Tru64 {};
-
-#else //!FULL_SYSTEM
-
 #include <sys/stat.h>
 #include <sys/types.h>
 #if defined(__OpenBSD__) || defined(__APPLE__) || defined(__FreeBSD__)
@@ -1225,6 +1219,4 @@ class Tru64_PreF64 : public Tru64
     }
 };
 
-#endif // FULL_SYSTEM
-
 #endif // __TRU64_HH__