Automated merge with ssh://daystrom.m5sim.org//repo/m5

--HG--
extra : convert_revision : 7922848bb1145bcb2ee07d672d21cfe2dd98fc03

27 files changed, 1361 insertions, 315 deletions

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 44c13ef78..bcc80eaf9 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -177,19 +177,12 @@ def makeLinuxX86System(mem_mode, mdesc = None):
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
 
-    # Serial port and console
-    self.console = SimConsole()
-    self.com_1 = Uart8250()
-    self.com_1.pio_addr = x86IOAddress(0x3f8)
-    self.com_1.pio = self.iobus.port
-    self.com_1.sim_console = self.console
-
     # Command line
     self.boot_osflags = 'earlyprintk=ttyS0'
 
     # Platform
-    self.opteron = Opteron()
-    self.opteron.attachIO(self.iobus)
+    self.pc = PC()
+    self.pc.attachIO(self.iobus)
 
     self.intrctrl = IntrControl()
 
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index d605ce218..f46279c81 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -90,6 +90,18 @@ namespace X86ISA
 
     const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
     const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
+
+    static inline Addr
+    x86IOAddress(const uint32_t port)
+    {
+        return PhysAddrPrefixIO | port;
+    }
+
+    static inline Addr
+    x86PciConfigAddress(const uint32_t addr)
+    {
+        return PhysAddrPrefixPciConfig | addr;
+    }
 }
 
 #endif //__ARCH_X86_X86TRAITS_HH__
diff --git a/src/dev/SConscript b/src/dev/SConscript
index 0aba8ac35..ee7adb8c8 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -56,6 +56,7 @@ if env['FULL_SYSTEM']:
     Source('ide_disk.cc')
     Source('io_device.cc')
     Source('isa_fake.cc')
+    Source('mc146818.cc')
     Source('ns_gige.cc')
     Source('pciconfigall.cc')
     Source('pcidev.cc')
@@ -84,6 +85,7 @@ if env['FULL_SYSTEM']:
     TraceFlag('IdeCtrl')
     TraceFlag('IdeDisk')
     TraceFlag('IsaFake')
+    TraceFlag('MC146818')
     TraceFlag('PCIDEV')
     TraceFlag('PciConfigAll')
     TraceFlag('SimpleDisk')
diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript
index 2292c3c57..6bd26a9b1 100644
--- a/src/dev/alpha/SConscript
+++ b/src/dev/alpha/SConscript
@@ -42,5 +42,4 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
     Source('tsunami_pchip.cc')
 
     TraceFlag('AlphaConsole')
-    TraceFlag('MC146818')
     TraceFlag('Tsunami')
diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc
index 710aca48d..88999ecc5 100644
--- a/src/dev/alpha/tsunami_io.cc
+++ b/src/dev/alpha/tsunami_io.cc
@@ -57,157 +57,9 @@ using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami,
-                    const TsunamiIO::Params *p)
-    : _name(n), event(tsunami, p->frequency), addr(0)
+TsunamiIO::TsunamiRTC::TsunamiRTC(const string &n, const TsunamiIOParams *p) :
+    MC146818(n, p->time, p->year_is_bcd, p->frequency), tsunami(p->tsunami)
 {
-    memset(clock_data, 0, sizeof(clock_data));
-    stat_regA = RTCA_32768HZ | RTCA_1024HZ;
-    stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
-
-    year = p->time.tm_year;
-
-    if (p->year_is_bcd) {
-        // The datasheet says that the year field can be either BCD or
-        // years since 1900.  Linux seems to be happy with years since
-        // 1900.
-        year = year % 100;
-        int tens = year / 10;
-        int ones = year % 10;
-        year = (tens << 4) + ones;
-    }
-
-    // Unix is 0-11 for month, data seet says start at 1
-    mon = p->time.tm_mon + 1;
-    mday = p->time.tm_mday;
-    hour = p->time.tm_hour;
-    min = p->time.tm_min;
-    sec = p->time.tm_sec;
-
-    // Datasheet says 1 is sunday
-    wday = p->time.tm_wday + 1;
-
-    DPRINTFN("Real-time clock set to %s", asctime(&p->time));
-}
-
-void
-TsunamiIO::RTC::writeAddr(const uint8_t data)
-{
-    if (data <= RTC_STAT_REGD)
-        addr = data;
-    else
-        panic("RTC addresses over 0xD are not implemented.\n");
-}
-
-void
-TsunamiIO::RTC::writeData(const uint8_t data)
-{
-    if (addr < RTC_STAT_REGA)
-        clock_data[addr] = data;
-    else {
-        switch (addr) {
-          case RTC_STAT_REGA:
-            if (data != (RTCA_32768HZ | RTCA_1024HZ))
-                panic("Unimplemented RTC register A value write!\n");
-            stat_regA = data;
-            break;
-          case RTC_STAT_REGB:
-            if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
-                panic("Write to RTC reg B bits that are not implemented!\n");
-
-            if (data & RTCB_PRDC_IE) {
-                if (!event.scheduled())
-                    event.scheduleIntr();
-            } else {
-                if (event.scheduled())
-                    event.deschedule();
-            }
-            stat_regB = data;
-            break;
-          case RTC_STAT_REGC:
-          case RTC_STAT_REGD:
-            panic("RTC status registers C and D are not implemented.\n");
-            break;
-        }
-    }
-}
-
-uint8_t
-TsunamiIO::RTC::readData()
-{
-    if (addr < RTC_STAT_REGA)
-        return clock_data[addr];
-    else {
-        switch (addr) {
-          case RTC_STAT_REGA:
-            // toggle UIP bit for linux
-            stat_regA ^= RTCA_UIP;
-            return stat_regA;
-            break;
-          case RTC_STAT_REGB:
-            return stat_regB;
-            break;
-          case RTC_STAT_REGC:
-          case RTC_STAT_REGD:
-            return 0x00;
-            break;
-          default:
-            panic("Shouldn't be here");
-        }
-    }
-}
-
-void
-TsunamiIO::RTC::serialize(const string &base, ostream &os)
-{
-    paramOut(os, base + ".addr", addr);
-    arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
-    paramOut(os, base + ".stat_regA", stat_regA);
-    paramOut(os, base + ".stat_regB", stat_regB);
-}
-
-void
-TsunamiIO::RTC::unserialize(const string &base, Checkpoint *cp,
-                            const string &section)
-{
-    paramIn(cp, section, base + ".addr", addr);
-    arrayParamIn(cp, section, base + ".clock_data", clock_data,
-                 sizeof(clock_data));
-    paramIn(cp, section, base + ".stat_regA", stat_regA);
-    paramIn(cp, section, base + ".stat_regB", stat_regB);
-
-    // We're not unserializing the event here, but we need to
-    // rescehedule the event since curTick was moved forward by the
-    // checkpoint
-    event.reschedule(curTick + event.interval);
-}
-
-TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami*t, Tick i)
-    : Event(&mainEventQueue), tsunami(t), interval(i)
-{
-    DPRINTF(MC146818, "RTC Event Initilizing\n");
-    schedule(curTick + interval);
-}
-
-void
-TsunamiIO::RTC::RTCEvent::scheduleIntr()
-{
-  schedule(curTick + interval);
-}
-
-void
-TsunamiIO::RTC::RTCEvent::process()
-{
-    DPRINTF(MC146818, "RTC Timer Interrupt\n");
-    schedule(curTick + interval);
-    //Actually interrupt the processor here
-    tsunami->cchip->postRTC();
-}
-
-const char *
-TsunamiIO::RTC::RTCEvent::description() const
-{
-    return "tsunami RTC interrupt";
 }
 
 TsunamiIO::PITimer::PITimer(const string &name)
@@ -436,7 +288,7 @@ TsunamiIO::PITimer::Counter::CounterEvent::description() const
 
 TsunamiIO::TsunamiIO(const Params *p)
     : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
-      rtc(p->name + ".rtc", p->tsunami, p)
+      rtc(p->name + ".rtc", p)
 {
     pioSize = 0x100;
 
@@ -495,7 +347,7 @@ TsunamiIO::read(PacketPtr pkt)
             pkt->set(pitimer.counter2.read());
             break;
           case TSDEV_RTC_DATA:
-            pkt->set(rtc.readData());
+            pkt->set(rtc.readData(rtcAddr));
             break;
           case TSDEV_CTRL_PORTB:
             if (pitimer.counter2.outputHigh())
@@ -573,10 +425,10 @@ TsunamiIO::write(PacketPtr pkt)
         pitimer.writeControl(pkt->get<uint8_t>());
         break;
       case TSDEV_RTC_ADDR:
-        rtc.writeAddr(pkt->get<uint8_t>());
+        rtcAddr = pkt->get<uint8_t>();
         break;
       case TSDEV_RTC_DATA:
-        rtc.writeData(pkt->get<uint8_t>());
+        rtc.writeData(rtcAddr, pkt->get<uint8_t>());
         break;
       case TSDEV_KBD:
       case TSDEV_DMA1_CMND:
@@ -623,6 +475,7 @@ TsunamiIO::clearPIC(uint8_t bitvector)
 void
 TsunamiIO::serialize(ostream &os)
 {
+    SERIALIZE_SCALAR(rtcAddr);
     SERIALIZE_SCALAR(timerData);
     SERIALIZE_SCALAR(mask1);
     SERIALIZE_SCALAR(mask2);
@@ -639,6 +492,7 @@ TsunamiIO::serialize(ostream &os)
 void
 TsunamiIO::unserialize(Checkpoint *cp, const string &section)
 {
+    UNSERIALIZE_SCALAR(rtcAddr);
     UNSERIALIZE_SCALAR(timerData);
     UNSERIALIZE_SCALAR(mask1);
     UNSERIALIZE_SCALAR(mask2);
diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh
index 05c4ee910..3972efa48 100644
--- a/src/dev/alpha/tsunami_io.hh
+++ b/src/dev/alpha/tsunami_io.hh
@@ -39,6 +39,7 @@
 
 #include "base/range.hh"
 #include "dev/alpha/tsunami.hh"
+#include "dev/mc146818.hh"
 #include "dev/io_device.hh"
 #include "params/TsunamiIO.hh"
 #include "sim/eventq.hh"
@@ -53,91 +54,19 @@ class TsunamiIO : public BasicPioDevice
     struct tm tm;
 
   protected:
-    /** Real-Time Clock (MC146818) */
-    class RTC
-    {
-      private:
-        /** Event for RTC periodic interrupt */
-        struct RTCEvent : public Event
-        {
-            /** A pointer back to tsunami to create interrupt the processor. */
-            Tsunami* tsunami;
-            Tick interval;
-
-            RTCEvent(Tsunami* t, Tick i);
-
-            /** Schedule the RTC periodic interrupt */
-            void scheduleIntr();
-
-            /** Event process to occur at interrupt*/
-            virtual void process();
-
-            /** Event description */
-            virtual const char *description() const;
-        };
-
-      private:
-        std::string _name;
-        const std::string &name() const { return _name; }
-
-        /** RTC periodic interrupt event */
-        RTCEvent event;
-
-        /** Current RTC register address/index */
-        int addr;
-
-        /** Data for real-time clock function */
-        union {
-            uint8_t clock_data[10];
-
-            struct {
-                uint8_t sec;
-                uint8_t sec_alrm;
-                uint8_t min;
-                uint8_t min_alrm;
-                uint8_t hour;
-                uint8_t hour_alrm;
-                uint8_t wday;
-                uint8_t mday;
-                uint8_t mon;
-                uint8_t year;
-            };
-        };
-
-        /** RTC status register A */
-        uint8_t stat_regA;
-
-        /** RTC status register B */
-        uint8_t stat_regB;
 
+    class TsunamiRTC : public MC146818
+    {
       public:
-        RTC(const std::string &name, Tsunami* tsunami,
-            const TsunamiIOParams *params);
-
-        /** RTC address port: write address of RTC RAM data to access */
-        void writeAddr(const uint8_t data);
-
-        /** RTC write data */
-        void writeData(const uint8_t data);
-
-        /** RTC read data */
-        uint8_t readData();
+        Tsunami * tsunami;
+        TsunamiRTC(const std::string &n, const TsunamiIOParams *p);
 
-        /**
-          * Serialize this object to the given output stream.
-          * @param base The base name of the counter object.
-          * @param os The stream to serialize to.
-          */
-        void serialize(const std::string &base, std::ostream &os);
-
-        /**
-         * Reconstruct the state of this object from a checkpoint.
-          * @param base The base name of the counter object.
-         * @param cp The checkpoint use.
-         * @param section The section name of this object
-         */
-        void unserialize(const std::string &base, Checkpoint *cp,
-                         const std::string &section);
+      protected:
+        void handleEvent()
+        {
+            //Actually interrupt the processor here
+            tsunami->cchip->postRTC();
+        }
     };
 
     /** Programmable Interval Timer (Intel 8254) */
@@ -296,7 +225,9 @@ class TsunamiIO : public BasicPioDevice
     /** Intel 8253 Periodic Interval Timer */
     PITimer pitimer;
 
-    RTC rtc;
+    TsunamiRTC rtc;
+
+    uint8_t rtcAddr;
 
     /** The interval is set via two writes to the PIT.
      * This variable contains a flag as to how many writes have happened, and
diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc
new file mode 100644
index 000000000..984422105
--- /dev/null
+++ b/src/dev/mc146818.cc
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Andrew Schultz
+ *          Miguel Serrano
+ */
+
+#include <sys/time.h>
+#include <time.h>
+
+#include <string>
+
+#include "base/time.hh"
+#include "base/trace.hh"
+#include "dev/mc146818.hh"
+#include "dev/rtcreg.h"
+
+using namespace std;
+
+MC146818::MC146818(const string &n, const struct tm time,
+        bool bcd, Tick frequency)
+    : _name(n), event(this, frequency)
+{
+    memset(clock_data, 0, sizeof(clock_data));
+    stat_regA = RTCA_32768HZ | RTCA_1024HZ;
+    stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
+
+    year = time.tm_year;
+
+    if (bcd) {
+        // The datasheet says that the year field can be either BCD or
+        // years since 1900.  Linux seems to be happy with years since
+        // 1900.
+        year = year % 100;
+        int tens = year / 10;
+        int ones = year % 10;
+        year = (tens << 4) + ones;
+    }
+
+    // Unix is 0-11 for month, data seet says start at 1
+    mon = time.tm_mon + 1;
+    mday = time.tm_mday;
+    hour = time.tm_hour;
+    min = time.tm_min;
+    sec = time.tm_sec;
+
+    // Datasheet says 1 is sunday
+    wday = time.tm_wday + 1;
+
+    DPRINTFN("Real-time clock set to %s", asctime(&time));
+}
+
+void
+MC146818::writeData(const uint8_t addr, const uint8_t data)
+{
+    if (addr < RTC_STAT_REGA)
+        clock_data[addr] = data;
+    else {
+        switch (addr) {
+          case RTC_STAT_REGA:
+            if (data != (RTCA_32768HZ | RTCA_1024HZ))
+                panic("Unimplemented RTC register A value write!\n");
+            stat_regA = data;
+            break;
+          case RTC_STAT_REGB:
+            if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
+                panic("Write to RTC reg B bits that are not implemented!\n");
+
+            if (data & RTCB_PRDC_IE) {
+                if (!event.scheduled())
+                    event.scheduleIntr();
+            } else {
+                if (event.scheduled())
+                    event.deschedule();
+            }
+            stat_regB = data;
+            break;
+          case RTC_STAT_REGC:
+          case RTC_STAT_REGD:
+            panic("RTC status registers C and D are not implemented.\n");
+            break;
+        }
+    }
+}
+
+uint8_t
+MC146818::readData(uint8_t addr)
+{
+    if (addr < RTC_STAT_REGA)
+        return clock_data[addr];
+    else {
+        switch (addr) {
+          case RTC_STAT_REGA:
+            // toggle UIP bit for linux
+            stat_regA ^= RTCA_UIP;
+            return stat_regA;
+            break;
+          case RTC_STAT_REGB:
+            return stat_regB;
+            break;
+          case RTC_STAT_REGC:
+          case RTC_STAT_REGD:
+            return 0x00;
+            break;
+          default:
+            panic("Shouldn't be here");
+        }
+    }
+}
+
+void
+MC146818::serialize(const string &base, ostream &os)
+{
+    arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
+    paramOut(os, base + ".stat_regA", stat_regA);
+    paramOut(os, base + ".stat_regB", stat_regB);
+}
+
+void
+MC146818::unserialize(const string &base, Checkpoint *cp,
+                      const string &section)
+{
+    arrayParamIn(cp, section, base + ".clock_data", clock_data,
+                 sizeof(clock_data));
+    paramIn(cp, section, base + ".stat_regA", stat_regA);
+    paramIn(cp, section, base + ".stat_regB", stat_regB);
+
+    // We're not unserializing the event here, but we need to
+    // rescehedule the event since curTick was moved forward by the
+    // checkpoint
+    event.reschedule(curTick + event.interval);
+}
+
+MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
+    : Event(&mainEventQueue), parent(_parent), interval(i)
+{
+    DPRINTF(MC146818, "RTC Event Initilizing\n");
+    schedule(curTick + interval);
+}
+
+void
+MC146818::RTCEvent::scheduleIntr()
+{
+  schedule(curTick + interval);
+}
+
+void
+MC146818::RTCEvent::process()
+{
+    DPRINTF(MC146818, "RTC Timer Interrupt\n");
+    schedule(curTick + interval);
+    parent->handleEvent();
+}
+
+const char *
+MC146818::RTCEvent::description() const
+{
+    return "RTC interrupt";
+}
diff --git a/src/dev/mc146818.hh b/src/dev/mc146818.hh
new file mode 100644
index 000000000..f91e462d9
--- /dev/null
+++ b/src/dev/mc146818.hh
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Andrew Schultz
+ *          Miguel Serrano
+ */
+
+#ifndef __DEV_MC146818_HH__
+#define __DEV_MC146818_HH__
+
+#include "base/range.hh"
+#include "sim/eventq.hh"
+
+/** Real-Time Clock (MC146818) */
+class MC146818
+{
+  protected:
+    virtual void handleEvent()
+    {
+        warn("No RTC event handler defined.\n");
+    }
+
+  private:
+    /** Event for RTC periodic interrupt */
+    struct RTCEvent : public Event
+    {
+        MC146818 * parent;
+        Tick interval;
+
+        RTCEvent(MC146818 * _parent, Tick i);
+
+        /** Schedule the RTC periodic interrupt */
+        void scheduleIntr();
+
+        /** Event process to occur at interrupt*/
+        virtual void process();
+
+        /** Event description */
+        virtual const char *description() const;
+    };
+
+  private:
+    std::string _name;
+    const std::string &name() const { return _name; }
+
+    /** RTC periodic interrupt event */
+    RTCEvent event;
+
+    /** Data for real-time clock function */
+    union {
+        uint8_t clock_data[10];
+
+        struct {
+            uint8_t sec;
+            uint8_t sec_alrm;
+            uint8_t min;
+            uint8_t min_alrm;
+            uint8_t hour;
+            uint8_t hour_alrm;
+            uint8_t wday;
+            uint8_t mday;
+            uint8_t mon;
+            uint8_t year;
+        };
+    };
+
+    /** RTC status register A */
+    uint8_t stat_regA;
+
+    /** RTC status register B */
+    uint8_t stat_regB;
+
+  public:
+    virtual ~MC146818()
+    {}
+
+    MC146818(const std::string &name, const struct tm time,
+            bool bcd, Tick frequency);
+
+    /** RTC write data */
+    void writeData(const uint8_t addr, const uint8_t data);
+
+    /** RTC read data */
+    uint8_t readData(const uint8_t addr);
+
+    /**
+      * Serialize this object to the given output stream.
+      * @param base The base name of the counter object.
+      * @param os The stream to serialize to.
+      */
+    void serialize(const std::string &base, std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param base The base name of the counter object.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
+    void unserialize(const std::string &base, Checkpoint *cp,
+                     const std::string &section);
+};
+
+#endif // __DEV_MC146818_HH__
diff --git a/src/dev/rtcreg.h b/src/dev/rtcreg.h
index 37255777b..b1406c464 100644
--- a/src/dev/rtcreg.h
+++ b/src/dev/rtcreg.h
@@ -30,32 +30,32 @@
  *          Nathan Binkert
  */
 
-#define RTC_SEC                 0x00
-#define RTC_SEC_ALRM            0x01
-#define RTC_MIN                 0x02
-#define RTC_MIN_ALRM            0x03
-#define RTC_HR                  0x04
-#define RTC_HR_ALRM             0x05
-#define RTC_DOW                 0x06
-#define RTC_DOM                 0x07
-#define RTC_MON                 0x08
-#define RTC_YEAR                0x09
+static const int RTC_SEC = 0x00;
+static const int RTC_SEC_ALRM = 0x01;
+static const int RTC_MIN = 0x02;
+static const int RTC_MIN_ALRM = 0x03;
+static const int RTC_HR = 0x04;
+static const int RTC_HR_ALRM = 0x05;
+static const int RTC_DOW = 0x06;
+static const int RTC_DOM = 0x07;
+static const int RTC_MON = 0x08;
+static const int RTC_YEAR = 0x09;
 
-#define RTC_STAT_REGA           0x0A
-#define  RTCA_1024HZ            0x06  /* 1024Hz periodic interrupt frequency */
-#define  RTCA_32768HZ           0x20  /* 22-stage divider, 32.768KHz timebase */
-#define  RTCA_UIP               0x80  /* 1 = date and time update in progress */
+static const int RTC_STAT_REGA = 0x0A;
+static const int RTCA_1024HZ = 0x06;  /* 1024Hz periodic interrupt frequency */
+static const int RTCA_32768HZ = 0x20; /* 22-stage divider, 32.768KHz timebase */
+static const int RTCA_UIP = 0x80;     /* 1 = date and time update in progress */
 
-#define RTC_STAT_REGB           0x0B
-#define  RTCB_DST               0x01  /* USA Daylight Savings Time enable */
-#define  RTCB_24HR              0x02  /* 0 = 12 hours, 1 = 24 hours */
-#define  RTCB_BIN               0x04  /* 0 = BCD, 1 = Binary coded time */
-#define  RTCB_SQWE              0x08  /* 1 = output sqare wave at SQW pin */
-#define  RTCB_UPDT_IE           0x10  /* 1 = enable update-ended interrupt */
-#define  RTCB_ALRM_IE           0x20  /* 1 = enable alarm interrupt */
-#define  RTCB_PRDC_IE           0x40  /* 1 = enable periodic clock interrupt */
-#define  RTCB_NO_UPDT           0x80  /* stop clock updates */
+static const int RTC_STAT_REGB = 0x0B;
+static const int RTCB_DST = 0x01;     /* USA Daylight Savings Time enable */
+static const int RTCB_24HR = 0x02;    /* 0 = 12 hours, 1 = 24 hours */
+static const int RTCB_BIN = 0x04;     /* 0 = BCD, 1 = Binary coded time */
+static const int RTCB_SQWE = 0x08;    /* 1 = output sqare wave at SQW pin */
+static const int RTCB_UPDT_IE = 0x10; /* 1 = enable update-ended interrupt */
+static const int RTCB_ALRM_IE = 0x20; /* 1 = enable alarm interrupt */
+static const int RTCB_PRDC_IE = 0x40; /* 1 = enable periodic clock interrupt */
+static const int RTCB_NO_UPDT = 0x80; /* stop clock updates */
 
-#define RTC_STAT_REGC           0x0C
-#define RTC_STAT_REGD           0x0D
+static const int RTC_STAT_REGC = 0x0C;
+static const int RTC_STAT_REGD = 0x0D;
 
diff --git a/src/dev/x86/Opteron.py b/src/dev/x86/Opteron.py
deleted file mode 100644
index cb015e2e7..000000000
--- a/src/dev/x86/Opteron.py
+++ /dev/null
@@ -1,18 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Uart import Uart8250
-from Platform import Platform
-from Pci import PciConfigAll
-from SimConsole import SimConsole
-
-class Opteron(Platform):
-    type = 'Opteron'
-    system = Param.System(Parent.any, "system")
-
-    pciconfig = PciConfigAll()
-
-    def attachIO(self, bus):
-        self.pciconfig.pio = bus.default
-        bus.responder_set = True
-        bus.responder = self.pciconfig
diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py
new file mode 100644
index 000000000..86ae4c3ba
--- /dev/null
+++ b/src/dev/x86/PC.py
@@ -0,0 +1,65 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Uart import Uart8250
+from Device import IsaFake
+from SouthBridge import SouthBridge
+from Platform import Platform
+from Pci import PciConfigAll
+from SimConsole import SimConsole
+
+def x86IOAddress(port):
+    IO_address_space_base = 0x8000000000000000
+    return IO_address_space_base + port;
+
+class PC(Platform):
+    type = 'PC'
+    system = Param.System(Parent.any, "system")
+
+    pciconfig = PciConfigAll()
+
+    south_bridge = SouthBridge()
+
+    # "Non-existant" port used for timing purposes by the linux kernel
+    i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+
+    # Serial port and console
+    console = SimConsole()
+    com_1 = Uart8250()
+    com_1.pio_addr = x86IOAddress(0x3f8)
+    com_1.sim_console = console
+
+    def attachIO(self, bus):
+        self.south_bridge.pio = bus.port
+        self.i_dont_exist.pio = bus.port
+        self.com_1.pio = bus.port
+        self.pciconfig.pio = bus.default
+        bus.responder_set = True
+        bus.responder = self.pciconfig
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index c500531b1..463344001 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -26,12 +26,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
-#          Gabe Black
+# Authors: Gabe Black
 
 Import('*')
 
 if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
-    SimObject('Opteron.py')
+    SimObject('PC.py')
 
-    Source('opteron.cc')
+    Source('pc.cc')
diff --git a/src/dev/x86/opteron.cc b/src/dev/x86/pc.cc
index ba46f2dfa..148ba92f7 100644
--- a/src/dev/x86/opteron.cc
+++ b/src/dev/x86/pc.cc
@@ -29,7 +29,7 @@
  */
 
 /** @file
- * Implementation of Opteron platform.
+ * Implementation of PC platform.
  */
 
 #include <deque>
@@ -39,13 +39,13 @@
 #include "arch/x86/x86_traits.hh"
 #include "cpu/intr_control.hh"
 #include "dev/simconsole.hh"
-#include "dev/x86/opteron.hh"
+#include "dev/x86/pc.hh"
 #include "sim/system.hh"
 
 using namespace std;
 using namespace TheISA;
 
-Opteron::Opteron(const Params *p)
+PC::PC(const Params *p)
     : Platform(p), system(p->system)
 {
     // set the back pointer from the system to myself
@@ -53,40 +53,40 @@ Opteron::Opteron(const Params *p)
 }
 
 Tick
-Opteron::intrFrequency()
+PC::intrFrequency()
 {
     panic("Need implementation\n");
     M5_DUMMY_RETURN
 }
 
 void
-Opteron::postConsoleInt()
+PC::postConsoleInt()
 {
     warn_once("Don't know what interrupt to post for console.\n");
     //panic("Need implementation\n");
 }
 
 void
-Opteron::clearConsoleInt()
+PC::clearConsoleInt()
 {
     warn_once("Don't know what interrupt to clear for console.\n");
     //panic("Need implementation\n");
 }
 
 void
-Opteron::postPciInt(int line)
+PC::postPciInt(int line)
 {
     panic("Need implementation\n");
 }
 
 void
-Opteron::clearPciInt(int line)
+PC::clearPciInt(int line)
 {
     panic("Need implementation\n");
 }
 
 Addr
-Opteron::pciToDma(Addr pciAddr) const
+PC::pciToDma(Addr pciAddr) const
 {
     panic("Need implementation\n");
     M5_DUMMY_RETURN
@@ -94,7 +94,7 @@ Opteron::pciToDma(Addr pciAddr) const
 
 
 Addr
-Opteron::calcConfigAddr(int bus, int dev, int func)
+PC::calcConfigAddr(int bus, int dev, int func)
 {
     assert(func < 8);
     assert(dev < 32);
@@ -102,8 +102,8 @@ Opteron::calcConfigAddr(int bus, int dev, int func)
     return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
 }
 
-Opteron *
-OpteronParams::create()
+PC *
+PCParams::create()
 {
-    return new Opteron(this);
+    return new PC(this);
 }
diff --git a/src/dev/x86/opteron.hh b/src/dev/x86/pc.hh
index 3026bce73..6e3a7f45e 100644
--- a/src/dev/x86/opteron.hh
+++ b/src/dev/x86/pc.hh
@@ -30,29 +30,29 @@
 
 /**
  * @file
- * Declaration of top level class for the Opteron platform chips. This class
+ * Declaration of top level class for PC platform components. This class
  * just retains pointers to all its children so the children can communicate.
  */
 
-#ifndef __DEV_Opteron_HH__
-#define __DEV_Opteron_HH__
+#ifndef __DEV_PC_HH__
+#define __DEV_PC_HH__
 
 #include "dev/platform.hh"
-#include "params/Opteron.hh"
+#include "params/PC.hh"
 
 class IdeController;
 class System;
 
-class Opteron : public Platform
+class PC : public Platform
 {
   public:
     /** Pointer to the system */
     System *system;
 
   public:
-    typedef OpteronParams Params;
+    typedef PCParams Params;
 
-    Opteron(const Params *p);
+    PC(const Params *p);
 
     /**
      * Return the interrupting frequency to AlphaAccess
@@ -89,4 +89,4 @@ class Opteron : public Platform
     virtual Addr calcConfigAddr(int bus, int dev, int func);
 };
 
-#endif // __DEV_OPTERON_HH__
+#endif // __DEV_PC_HH__
diff --git a/src/dev/x86/south_bridge/SConscript b/src/dev/x86/south_bridge/SConscript
new file mode 100644
index 000000000..a7cb77b9b
--- /dev/null
+++ b/src/dev/x86/south_bridge/SConscript
@@ -0,0 +1,42 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+Import('*')
+
+if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
+    # Main device
+    SimObject('SouthBridge.py')
+    Source('south_bridge.cc')
+
+    # Sub devices
+    Source('cmos.cc')
+    Source('i8254.cc')
+    Source('i8259.cc')
+    Source('speaker.cc')
diff --git a/src/dev/x86/south_bridge/SouthBridge.py b/src/dev/x86/south_bridge/SouthBridge.py
new file mode 100644
index 000000000..bec3c4223
--- /dev/null
+++ b/src/dev/x86/south_bridge/SouthBridge.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Device import PioDevice
+
+class SouthBridge(PioDevice):
+    type = 'SouthBridge'
+    pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
diff --git a/src/dev/x86/south_bridge/cmos.cc b/src/dev/x86/south_bridge/cmos.cc
new file mode 100644
index 000000000..164b23d84
--- /dev/null
+++ b/src/dev/x86/south_bridge/cmos.cc
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/cmos.hh"
+#include "mem/packet_access.hh"
+
+Tick
+X86ISA::Cmos::read(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - addrRange.start)
+    {
+      case 0x0:
+        pkt->set(address);
+        break;
+      case 0x1:
+        pkt->set(readRegister(address));
+        break;
+      default:
+        panic("Read from undefined CMOS port.\n");
+    }
+    return latency;
+}
+
+Tick
+X86ISA::Cmos::write(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - addrRange.start)
+    {
+      case 0x0:
+        address = pkt->get<uint8_t>();
+        break;
+      case 0x1:
+        writeRegister(address, pkt->get<uint8_t>());
+        break;
+      default:
+        panic("Write to undefined CMOS port.\n");
+    }
+    return latency;
+}
+
+uint8_t
+X86ISA::Cmos::readRegister(uint8_t reg)
+{
+    assert(reg < numRegs);
+    if (reg <= 0xD) {
+        return rtc.readData(reg);
+    } else {
+        warn("Reading non-volitile CMOS address %x as %x.\n", reg, regs[reg]);
+    }
+    return regs[reg];
+}
+
+void
+X86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val)
+{
+    assert(reg < numRegs);
+    if (reg <= 0xD) {
+        rtc.writeData(reg, val);
+        return;
+    } else {
+        warn("Writing non-volitile CMOS address %x with %x.\n", reg, val);
+    }
+    regs[reg] = val;
+}
diff --git a/src/dev/x86/south_bridge/cmos.hh b/src/dev/x86/south_bridge/cmos.hh
new file mode 100644
index 000000000..6fd7613bc
--- /dev/null
+++ b/src/dev/x86/south_bridge/cmos.hh
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_CMOS_HH__
+#define __DEV_X86_SOUTH_BRIDGE_CMOS_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/mc146818.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class Cmos : public SubDevice
+{
+  protected:
+    uint8_t address;
+
+    struct tm foo_time;
+
+    static const int numRegs = 128;
+
+    uint8_t regs[numRegs];
+
+    uint8_t readRegister(uint8_t reg);
+    void writeRegister(uint8_t reg, uint8_t val);
+
+    class X86RTC : public MC146818
+    {
+      public:
+        X86RTC(const std::string &n, const struct tm time,
+                bool bcd, Tick frequency) : MC146818(n, time, bcd, frequency)
+        {
+        }
+      protected:
+        void handleEvent()
+        {
+            return;
+        }
+    } rtc;
+
+  public:
+
+    Cmos() : rtc("rtc", foo_time, true, 5000000000)
+    {
+        memset(regs, 0, numRegs * sizeof(uint8_t));
+        address = 0;
+    }
+
+    Cmos(Tick _latency) : SubDevice(_latency),
+        rtc("rtc", foo_time, true, 5000000000)
+    {
+        memset(regs, 0, numRegs * sizeof(uint8_t));
+        address = 0;
+    }
+
+    Cmos(Addr start, Addr size, Tick _latency) :
+        SubDevice(start, size, _latency),
+        rtc("rtc", foo_time, true, 5000000000)
+    {
+        memset(regs, 0, numRegs * sizeof(uint8_t));
+        address = 0;
+    }
+
+    Tick read(PacketPtr pkt);
+
+    Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_CMOS_HH__
diff --git a/src/dev/x86/south_bridge/i8254.cc b/src/dev/x86/south_bridge/i8254.cc
new file mode 100644
index 000000000..fb6723a51
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8254.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/i8254.hh"
+#include "mem/packet_access.hh"
+
+Tick
+X86ISA::I8254::read(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - addrRange.start)
+    {
+      case 0x0:
+        warn("Reading from timer 0 counter.\n");
+        break;
+      case 0x1:
+        warn("Reading from timer 1 counter.\n");
+        break;
+      case 0x2:
+        warn("Reading from timer 2 counter.\n");
+        break;
+      case 0x3:
+        fatal("Reading from timer control word which is read only.\n");
+        break;
+      default:
+        panic("Read from undefined i8254 register.\n");
+    }
+    return SubDevice::read(pkt);
+}
+
+Tick
+X86ISA::I8254::write(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - addrRange.start)
+    {
+      case 0x0:
+        warn("Writing to timer 0 counter.\n");
+        break;
+      case 0x1:
+        warn("Writing to timer 1 counter.\n");
+        break;
+      case 0x2:
+        warn("Writing to timer 2 counter.\n");
+        break;
+      case 0x3:
+        processControlWord(pkt->get<uint8_t>());
+        return latency;
+      default:
+        panic("Write to undefined i8254 register.\n");
+    }
+    return SubDevice::write(pkt);
+}
+
+void
+X86ISA::I8254::processControlWord(uint8_t word)
+{
+    warn("I8254 received control word %x.\n", word);
+}
diff --git a/src/dev/x86/south_bridge/i8254.hh b/src/dev/x86/south_bridge/i8254.hh
new file mode 100644
index 000000000..f246fd8e4
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8254.hh
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_I8254_HH__
+#define __DEV_X86_SOUTH_BRIDGE_I8254_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class I8254 : public SubDevice
+{
+  protected:
+    void processControlWord(uint8_t word);
+
+  public:
+
+    I8254()
+    {}
+    I8254(Tick _latency) : SubDevice(_latency)
+    {}
+    I8254(Addr start, Addr size, Tick _latency) :
+        SubDevice(start, size, _latency)
+    {}
+
+    Tick read(PacketPtr pkt);
+
+    Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__
diff --git a/src/dev/x86/south_bridge/i8259.cc b/src/dev/x86/south_bridge/i8259.cc
new file mode 100644
index 000000000..0cf83dece
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8259.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/i8259.hh"
+
+Tick
+X86ISA::I8259::read(PacketPtr pkt)
+{
+    warn("Reading from PIC device.\n");
+    return SubDevice::read(pkt);
+}
+
+Tick
+X86ISA::I8259::write(PacketPtr pkt)
+{
+    warn("Writing to PIC device.\n");
+    return SubDevice::write(pkt);
+}
diff --git a/src/dev/x86/south_bridge/i8259.hh b/src/dev/x86/south_bridge/i8259.hh
new file mode 100644
index 000000000..3fda75dfb
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8259.hh
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_I8259_HH__
+#define __DEV_X86_SOUTH_BRIDGE_I8259_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class I8259 : public SubDevice
+{
+  public:
+
+    I8259()
+    {}
+    I8259(Tick _latency) : SubDevice(_latency)
+    {}
+    I8259(Addr start, Addr size, Tick _latency) :
+        SubDevice(start, size, _latency)
+    {}
+
+    Tick read(PacketPtr pkt);
+
+    Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_I8259_HH__
diff --git a/src/dev/x86/south_bridge/south_bridge.cc b/src/dev/x86/south_bridge/south_bridge.cc
new file mode 100644
index 000000000..f25b3b811
--- /dev/null
+++ b/src/dev/x86/south_bridge/south_bridge.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/south_bridge.hh"
+
+using namespace X86ISA;
+
+void
+SouthBridge::addDevice(X86ISA::SubDevice & sub)
+{
+    rangeList.push_back(sub.addrRange);
+    rangeMap.insert(sub.addrRange, &sub);
+}
+
+void
+SouthBridge::addressRanges(AddrRangeList &range_list)
+{
+    range_list = rangeList;
+}
+
+Tick
+SouthBridge::read(PacketPtr pkt)
+{
+    RangeMapIt sub =
+        rangeMap.find(RangeSize(pkt->getAddr(), 1));
+    assert(sub != rangeMap.end());
+    return sub->second->read(pkt);
+}
+
+Tick
+SouthBridge::write(PacketPtr pkt)
+{
+    RangeMapIt sub =
+        rangeMap.find(RangeSize(pkt->getAddr(), 1));
+    assert(sub != rangeMap.end());
+    return sub->second->write(pkt);
+}
+
+SouthBridge::SouthBridge(const Params *p) : PioDevice(p),
+    pic1(0x20, 2, p->pio_latency),
+    pic2(0xA0, 2, p->pio_latency),
+    pit(0x40, 4, p->pio_latency),
+    cmos(0x70, 2, p->pio_latency),
+    speaker(0x61, 1, p->pio_latency)
+{
+    addDevice(pic1);
+    addDevice(pic2);
+    addDevice(pit);
+    addDevice(cmos);
+    addDevice(speaker);
+}
+
+SouthBridge *
+SouthBridgeParams::create()
+{
+    return new SouthBridge(this);
+}
diff --git a/src/dev/x86/south_bridge/south_bridge.hh b/src/dev/x86/south_bridge/south_bridge.hh
new file mode 100644
index 000000000..28936fb91
--- /dev/null
+++ b/src/dev/x86/south_bridge/south_bridge.hh
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
+
+#include "base/range_map.hh"
+#include "dev/io_device.hh"
+#include "dev/x86/south_bridge/cmos.hh"
+#include "dev/x86/south_bridge/i8254.hh"
+#include "dev/x86/south_bridge/i8259.hh"
+#include "dev/x86/south_bridge/speaker.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+#include "params/SouthBridge.hh"
+
+class SouthBridge : public PioDevice
+{
+  protected:
+    // PICs
+    X86ISA::I8259 pic1;
+    X86ISA::I8259 pic2;
+
+    // I8254 Programmable Interval Timer
+    X86ISA::I8254 pit;
+
+    // CMOS apperature
+    X86ISA::Cmos cmos;
+
+    // PC speaker
+    X86ISA::Speaker speaker;
+
+    AddrRangeList rangeList;
+
+    typedef range_map<Addr, X86ISA::SubDevice *> RangeMap;
+    typedef RangeMap::iterator RangeMapIt;
+    RangeMap rangeMap;
+
+
+    void addDevice(X86ISA::SubDevice &);
+
+  public:
+    void addressRanges(AddrRangeList &range_list);
+
+    Tick read(PacketPtr pkt);
+    Tick write(PacketPtr pkt);
+
+    typedef SouthBridgeParams Params;
+    SouthBridge(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+};
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
diff --git a/src/dev/x86/south_bridge/speaker.cc b/src/dev/x86/south_bridge/speaker.cc
new file mode 100644
index 000000000..734dba4c2
--- /dev/null
+++ b/src/dev/x86/south_bridge/speaker.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "base/bitunion.hh"
+#include "dev/x86/south_bridge/speaker.hh"
+#include "mem/packet_access.hh"
+
+BitUnion8(SpeakerControl)
+    Bitfield<0> gate;
+    Bitfield<1> speaker;
+    Bitfield<5> timer;
+EndBitUnion(SpeakerControl)
+
+Tick
+X86ISA::Speaker::read(PacketPtr pkt)
+{
+    assert(pkt->getAddr() == addrRange.start);
+    assert(pkt->getSize() == 1);
+    SpeakerControl val = 0xFF;
+    warn("Reading from speaker device: gate %s, speaker %s, output %s.\n",
+            val.gate ? "on" : "off",
+            val.speaker ? "on" : "off",
+            val.timer ? "on" : "off");
+    pkt->set((uint8_t)val);
+    return latency;
+}
+
+Tick
+X86ISA::Speaker::write(PacketPtr pkt)
+{
+    assert(pkt->getAddr() == addrRange.start);
+    assert(pkt->getSize() == 1);
+    SpeakerControl val = pkt->get<uint8_t>();
+    warn("Writing to speaker device: gate %s, speaker %s.\n",
+            val.gate ? "on" : "off", val.speaker ? "on" : "off");
+    return latency;
+}
diff --git a/src/dev/x86/south_bridge/speaker.hh b/src/dev/x86/south_bridge/speaker.hh
new file mode 100644
index 000000000..df738e42b
--- /dev/null
+++ b/src/dev/x86/south_bridge/speaker.hh
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class Speaker : public SubDevice
+{
+  public:
+
+    Speaker()
+    {}
+    Speaker(Tick _latency) : SubDevice(_latency)
+    {}
+    Speaker(Addr start, Addr size, Tick _latency) :
+        SubDevice(start, size, _latency)
+    {}
+
+    Tick read(PacketPtr pkt);
+
+    Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
diff --git a/src/dev/x86/south_bridge/sub_device.hh b/src/dev/x86/south_bridge/sub_device.hh
new file mode 100644
index 000000000..3cc51bdd9
--- /dev/null
+++ b/src/dev/x86/south_bridge/sub_device.hh
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "mem/packet.hh"
+
+namespace X86ISA
+{
+
+class SubDevice
+{
+  public:
+
+    Range<Addr> addrRange;
+    Tick latency;
+
+    virtual
+    ~SubDevice()
+    {}
+
+    SubDevice()
+    {}
+    SubDevice(Tick _latency) : latency(_latency)
+    {}
+    SubDevice(Addr start, Addr size, Tick _latency) :
+        addrRange(RangeSize(x86IOAddress(start), size)), latency(_latency)
+    {}
+
+    virtual Tick
+    read(PacketPtr pkt)
+    {
+        assert(pkt->getSize() <= 4);
+        pkt->allocate();
+        const uint32_t neg1 = -1;
+        pkt->setData((uint8_t *)(&neg1));
+        return latency;
+    }
+
+    virtual Tick
+    write(PacketPtr pkt)
+    {
+        return latency;
+    }
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__