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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-06-01 14:18:45 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-06-01 14:18:45 -0400 |
| commit | be0aef981943d123e0f4eb8c5520a74c1eb1002a (patch) | |
| tree | 84a847d42f203bf8e5f57e19c40af37091535960 | |
| parent | a7fe9345eefa106c12630eb92df5dc956d94820c (diff) | |
| parent | d8f676996222dfc2d2666bdc88499c58f1c1246c (diff) | |
| download | gem5-be0aef981943d123e0f4eb8c5520a74c1eb1002a.tar.xz | |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
src/cpu/simple/base.cc:
hand merge vincent/gabe/my changes to cast sizeof() to a 64bit int
--HG--
extra : convert_revision : eb989b4d65d08057df1777c04b8ee2cfa75a2695
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 4 | ||||
| -rw-r--r-- | src/cpu/simple/base.cc | 8 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index e16f97558..895b4a46c 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1151,10 +1151,14 @@ DefaultFetch<Impl>::fetch(bool &status_change) DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, instruction->staticInst->disassemble(fetch_PC)); +#if TRACING_ON instruction->traceData = Trace::getInstRecord(curTick, cpu->tcBase(tid), instruction->staticInst, instruction->readPC()); +#elif + instruction->traceData = NULL; +#endif ///FIXME This needs to be more robust in dealing with delay slots #if !ISA_HAS_DELAY_SLOT diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 6145b13a1..da50a3eb0 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -329,7 +329,7 @@ BaseSimpleCPU::checkForInterrupts() Fault BaseSimpleCPU::setupFetchRequest(Request *req) { - uint64_t threadPC = thread->readPC(); + Addr threadPC = thread->readPC(); // set up memory request for instruction fetch #if ISA_HAS_DELAY_SLOT @@ -340,8 +340,8 @@ BaseSimpleCPU::setupFetchRequest(Request *req) thread->readNextPC()); #endif - const Addr PCMask = ~(sizeof(MachInst) - 1); - Addr fetchPC = thread->readPC() + fetchOffset; + const Addr PCMask = ~((Addr)sizeof(MachInst) - 1); + Addr fetchPC = threadPC + fetchOffset; req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC); Fault fault = thread->translateInstReq(req); @@ -380,7 +380,7 @@ BaseSimpleCPU::preExecute() //This should go away once the constructor can be set up properly predecoder.setTC(thread->getTC()); //If more fetch data is needed, pass it in. - const Addr PCMask = ~(sizeof(MachInst) - 1); + const Addr PCMask = ~((Addr)sizeof(MachInst) - 1); if(predecoder.needMoreBytes()) predecoder.moreBytes((thread->readPC() & PCMask) + fetchOffset, 0, inst); |