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| author | Daniel Johnson <daniel.johnson@arm.com> | 2011-09-13 12:06:13 -0500 |
|---|---|---|
| committer | Daniel Johnson <daniel.johnson@arm.com> | 2011-09-13 12:06:13 -0500 |
| commit | cbb23a1d3c3df9d6bed34f50a0193b93319477e6 (patch) | |
| tree | 16d36e66e10d1fcf8b08b1686cedb12cbb65769a | |
| parent | 52d30813cac76b9dd69ed9c33bb4966f89c5e7a0 (diff) | |
| download | gem5-cbb23a1d3c3df9d6bed34f50a0193b93319477e6.tar.xz | |
ARM: update TLB to set request packet ASID field
| -rw-r--r-- | src/arch/arm/miscregs.hh | 5 | ||||
| -rw-r--r-- | src/arch/arm/tlb.cc | 2 | ||||
| -rw-r--r-- | src/arch/arm/tlb.hh | 2 |
3 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 5e5735de7..1f84fa4ca 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -436,6 +436,11 @@ namespace ArmISA Bitfield<31,30> or7; EndBitUnion(NMRR) + BitUnion32(CONTEXTIDR) + Bitfield<7,0> asid; + Bitfield<31,8> procid; + EndBitUnion(CONTEXTIDR) + BitUnion32(L2CTLR) Bitfield<2,0> sataRAMLatency; Bitfield<4,3> reserved_4_3; diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 942f85120..a03e445cf 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -467,6 +467,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, bool is_write = (mode == Write); bool is_priv = isPriv && !(flags & UserMode); + req->setAsid(contextId.asid); + DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", isPriv, flags & UserMode); // If this is a clrex instruction, provide a PA of 0 with no fault diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index f78e38a3d..3464e42b3 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -222,7 +222,7 @@ class TLB : public BaseTLB protected: SCTLR sctlr; bool isPriv; - uint32_t contextId; + CONTEXTIDR contextId; PRRR prrr; NMRR nmrr; uint32_t dacr; |