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authorAndreas Hansson <andreas.hansson@arm.com>2015-02-16 03:33:28 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-02-16 03:33:28 -0500
commitd0e1b8a19c6d58a49e5288938e9b12f3f10b9f51 (patch)
treef990864e7fb9ffaf11e3895e8337737941390aa2
parent07ce60bdfa57eedf00f533704b5a2da3fa01b553 (diff)
downloadgem5-d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51.tar.xz
arch: Make readMiscRegNoEffect const throughout
Finally took the plunge and made this apply to all ISAs, not just ARM.
-rw-r--r--src/arch/alpha/isa.cc2
-rw-r--r--src/arch/alpha/isa.hh2
-rw-r--r--src/arch/mips/isa.cc4
-rw-r--r--src/arch/mips/isa.hh4
-rw-r--r--src/arch/power/isa.hh2
-rw-r--r--src/arch/sparc/isa.cc2
-rw-r--r--src/arch/sparc/isa.hh2
-rw-r--r--src/arch/x86/isa.cc2
-rw-r--r--src/arch/x86/isa.hh2
-rw-r--r--src/cpu/checker/cpu.hh2
-rw-r--r--src/cpu/checker/thread_context.hh2
-rw-r--r--src/cpu/minor/exec_context.hh2
-rw-r--r--src/cpu/o3/cpu.cc2
-rw-r--r--src/cpu/o3/cpu.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context.hh2
-rw-r--r--src/cpu/simple/base.hh2
-rw-r--r--src/cpu/simple_thread.hh2
-rw-r--r--src/cpu/thread_context.hh4
18 files changed, 21 insertions, 21 deletions
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 95dfdedd6..20f039166 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -74,7 +74,7 @@ ISA::unserialize(Checkpoint *cp, const std::string &section)
MiscReg
-ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
switch (misc_reg) {
case MISCREG_FPCR:
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 36515b520..52e4e98be 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -73,7 +73,7 @@ namespace AlphaISA
public:
- MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
+ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 164f10d5d..a37f523d9 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -410,14 +410,14 @@ ISA::configCP()
}
inline unsigned
-ISA::getVPENum(ThreadID tid)
+ISA::getVPENum(ThreadID tid) const
{
TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
return tcBind.curVPE;
}
MiscReg
-ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index fea3f00ca..feb55e473 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -76,7 +76,7 @@ namespace MipsISA
void configCP();
- unsigned getVPENum(ThreadID tid);
+ unsigned getVPENum(ThreadID tid) const;
//////////////////////////////////////////////////////////
//
@@ -87,7 +87,7 @@ namespace MipsISA
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
void updateCP0ReadView(int misc_reg, ThreadID tid) { }
- MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
+ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
//template <class TC>
MiscReg readMiscReg(int misc_reg,
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index d19410037..aaf5bd92a 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -61,7 +61,7 @@ class ISA : public SimObject
}
MiscReg
- readMiscRegNoEffect(int misc_reg)
+ readMiscRegNoEffect(int misc_reg) const
{
fatal("Power does not currently have any misc regs defined\n");
return dummy;
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 4daf8775b..c9a3a33b4 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -173,7 +173,7 @@ ISA::clear()
}
MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
+ISA::readMiscRegNoEffect(int miscReg) const
{
// The three miscRegs are moved up from the switch statement
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 536deb69c..4551cf3c1 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -183,7 +183,7 @@ class ISA : public SimObject
public:
- MiscReg readMiscRegNoEffect(int miscReg);
+ MiscReg readMiscRegNoEffect(int miscReg) const;
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, const MiscReg val);
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index f65bc2392..f2d3ce42a 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -124,7 +124,7 @@ ISA::params() const
}
MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
+ISA::readMiscRegNoEffect(int miscReg) const
{
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 3ca771c61..a82b4ae2f 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -63,7 +63,7 @@ namespace X86ISA
ISA(Params *p);
const Params *params() const;
- MiscReg readMiscRegNoEffect(int miscReg);
+ MiscReg readMiscRegNoEffect(int miscReg) const;
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, MiscReg val);
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 49f44ff00..bed3b9e32 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -285,7 +285,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
MicroPC microPC() { return thread->microPC(); }
//////////////////////////////////////////
- MiscReg readMiscRegNoEffect(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg) const
{
return thread->readMiscRegNoEffect(misc_reg);
}
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index ccf0d3c1d..26d0dfa8b 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -275,7 +275,7 @@ class CheckerThreadContext : public ThreadContext
MicroPC microPC()
{ return actualTC->microPC(); }
- MiscReg readMiscRegNoEffect(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }
MiscReg readMiscReg(int misc_reg)
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 41345d3bd..80d5d9872 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -187,7 +187,7 @@ class ExecContext : public ::ExecContext
}
TheISA::MiscReg
- readMiscRegNoEffect(int misc_reg)
+ readMiscRegNoEffect(int misc_reg) const
{
return thread.readMiscRegNoEffect(misc_reg);
}
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b48c66c37..434bfd7da 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1205,7 +1205,7 @@ FullO3CPU<Impl>::verifyMemoryMode() const
template <class Impl>
TheISA::MiscReg
-FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
return this->isa[tid]->readMiscRegNoEffect(misc_reg);
}
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 09b7db867..5b33285c4 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -403,7 +403,7 @@ class FullO3CPU : public BaseO3CPU
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
+ TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 952d365bf..87d87900c 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -228,7 +228,7 @@ class O3ThreadContext : public ThreadContext
{ return cpu->microPC(thread->threadId()); }
/** Reads a miscellaneous register. */
- virtual MiscReg readMiscRegNoEffect(int misc_reg)
+ virtual MiscReg readMiscRegNoEffect(int misc_reg) const
{ return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
/** Reads a misc. register, including any side-effects the
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 7ace2204a..6e8b4a8c8 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -367,7 +367,7 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
Addr nextInstAddr() { return thread->nextInstAddr(); }
MicroPC microPC() { return thread->microPC(); }
- MiscReg readMiscRegNoEffect(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg) const
{
return thread->readMiscRegNoEffect(misc_reg);
}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 1f9e58ad9..e862385c5 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -372,7 +372,7 @@ class SimpleThread : public ThreadState
}
MiscReg
- readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
+ readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
{
return isa->readMiscRegNoEffect(misc_reg);
}
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 850ff9468..966924c50 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -225,7 +225,7 @@ class ThreadContext
virtual MicroPC microPC() = 0;
- virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+ virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
virtual MiscReg readMiscReg(int misc_reg) = 0;
@@ -429,7 +429,7 @@ class ProxyThreadContext : public ThreadContext
void setPredicate(bool val)
{ actualTC->setPredicate(val); }
- MiscReg readMiscRegNoEffect(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }
MiscReg readMiscReg(int misc_reg)