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authorGabe Black <gblack@eecs.umich.edu>2008-10-11 02:27:21 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-11 02:27:21 -0700
commitda7209ec93f3cdad11c02906357f06fa29652996 (patch)
tree54847aa95a3dc16e94d42f985722b5dac0322ad9
parent3af428606ad35e2cd40d5d1d39010ff732bfee4f (diff)
downloadgem5-da7209ec93f3cdad11c02906357f06fa29652996.tar.xz
CPU: Eliminate the hwrei function.
-rw-r--r--src/arch/alpha/ev5.cc17
-rw-r--r--src/arch/alpha/isa/decoder.isa11
-rw-r--r--src/arch/alpha/isa/main.isa2
-rw-r--r--src/cpu/checker/cpu.hh1
-rw-r--r--src/cpu/exec_context.hh4
-rw-r--r--src/cpu/o3/cpu.cc15
-rw-r--r--src/cpu/o3/cpu.hh3
-rw-r--r--src/cpu/o3/dyn_inst.hh2
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh22
-rw-r--r--src/cpu/ozone/cpu.hh1
-rw-r--r--src/cpu/ozone/cpu_impl.hh15
-rw-r--r--src/cpu/ozone/dyn_inst.hh1
-rw-r--r--src/cpu/ozone/dyn_inst_impl.hh15
-rw-r--r--src/cpu/simple/base.hh1
-rw-r--r--src/cpu/simple_thread.hh2
15 files changed, 12 insertions, 100 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 7dc02a611..eefe86bff 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -552,23 +552,6 @@ copyIprs(ThreadContext *src, ThreadContext *dest)
using namespace AlphaISA;
-Fault
-SimpleThread::hwrei()
-{
- if (!(readPC() & 0x3))
- return new UnimplementedOpcodeFault;
-
- setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
-
- if (!misspeculating()) {
- if (kernelStats)
- kernelStats->hwrei();
- }
-
- // FIXME: XXX check for interrupts? XXX
- return NoFault;
-}
-
/**
* Check for special simulator handling of specific PAL calls.
* If return value is false, actual PAL call will be suppressed.
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 270940df2..8025ba69f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -786,7 +786,16 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate {
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
- 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
+ 1: hw_rei({{
+ NPC = ExcAddr;
+ ThreadContext * tc = xc->tcBase();
+ if (!tc->misspeculating()) {
+ AlphaISA::Kernel::Statistics * kernelStats =
+ tc->getKernelStats();
+ if (kernelStats)
+ kernelStats->hwrei();
+ }
+ }}, IsSerializing, IsSerializeBefore);
}
// M5 special opcodes use the reserved 0x01 opcode space
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 5231712c8..078982697 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -69,6 +69,7 @@ output exec {{
#include <math.h>
#if FULL_SYSTEM
+#include "arch/alpha/kernel_stats.hh"
#include "sim/pseudo_inst.hh"
#endif
#include "arch/alpha/ipr.hh"
@@ -187,6 +188,7 @@ def operands {{
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
+ 'ExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 5b3c4582c..b234bf23f 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -336,7 +336,6 @@ class CheckerCPU : public BaseCPU
void translateDataReadReq(Request *req);
#if FULL_SYSTEM
- Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
#else
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 2b9fe4bcf..93192246c 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -144,10 +144,6 @@ class ExecContext {
void writeHint(Addr addr, int size, unsigned flags);
#if FULL_SYSTEM
- /** Somewhat Alpha-specific function that handles returning from
- * an error or interrupt. */
- Fault hwrei();
-
/**
* Check for special simulator handling of specific PAL calls. If
* return value is false, actual PAL call will be suppressed.
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index eb1115565..174f4a98d 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -906,21 +906,6 @@ FullO3CPU<Impl>::post_interrupt(int int_num, int index)
}
template <class Impl>
-Fault
-FullO3CPU<Impl>::hwrei(unsigned tid)
-{
-#if THE_ISA == ALPHA_ISA
- // Need to clear the lock flag upon returning from an interrupt.
- this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
-
- this->thread[tid]->kernelStats->hwrei();
-
- // FIXME: XXX check for interrupts? XXX
-#endif
- return NoFault;
-}
-
-template <class Impl>
bool
FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
{
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 406d965be..cdc1d2e58 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -414,9 +414,6 @@ class FullO3CPU : public BaseO3CPU
/** Posts an interrupt. */
void post_interrupt(int int_num, int index);
- /** HW return from error interrupt. */
- Fault hwrei(unsigned tid);
-
bool simPalCheck(int palFunc, unsigned tid);
/** Returns the Fault for any valid interrupt. */
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 292547b6b..ce59d802b 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -168,8 +168,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
}
#if FULL_SYSTEM
- /** Calls hardware return from error interrupt. */
- Fault hwrei();
/** Traps to handle specified fault. */
void trap(Fault fault);
bool simPalCheck(int palFunc);
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 6398a3afe..f85527f22 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -125,28 +125,6 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
#if FULL_SYSTEM
template <class Impl>
-Fault
-BaseO3DynInst<Impl>::hwrei()
-{
-#if THE_ISA == ALPHA_ISA
- // Can only do a hwrei when in pal mode.
- if (!(this->readPC() & 0x3))
- return new AlphaISA::UnimplementedOpcodeFault;
-
- // Set the next PC based on the value of the EXC_ADDR IPR.
- this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
- this->threadNumber));
-
- // Tell CPU to clear any state it needs to if a hwrei is taken.
- this->cpu->hwrei(this->threadNumber);
-#else
-
-#endif
- // FIXME: XXX check for interrupts? XXX
- return NoFault;
-}
-
-template <class Impl>
void
BaseO3DynInst<Impl>::trap(Fault fault)
{
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index c3ea33673..e95accdfd 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -510,7 +510,6 @@ class OzoneCPU : public BaseCPU
void dumpInsts() { frontEnd->dumpInsts(); }
#if FULL_SYSTEM
- Fault hwrei();
bool simPalCheck(int palFunc);
void processInterrupts();
#else
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index ceb980d4c..eb7b1a13f 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -669,21 +669,6 @@ OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
}
#else
template <class Impl>
-Fault
-OzoneCPU<Impl>::hwrei()
-{
- // Need to move this to ISA code
- // May also need to make this per thread
-
- lockFlag = false;
- lockAddrList.clear();
- thread.kernelStats->hwrei();
-
- // FIXME: XXX check for interrupts? XXX
- return NoFault;
-}
-
-template <class Impl>
void
OzoneCPU<Impl>::processInterrupts()
{
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index e138cbe13..deade9397 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -240,7 +240,6 @@ class OzoneDynInst : public BaseDynInst<Impl>
void setMiscReg(int misc_reg, const MiscReg &val);
#if FULL_SYSTEM
- Fault hwrei();
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 8519917f5..8fc5077a6 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -249,21 +249,6 @@ OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
#if FULL_SYSTEM
template <class Impl>
-Fault
-OzoneDynInst<Impl>::hwrei()
-{
- if (!(this->readPC() & 0x3))
- return new AlphaISA::UnimplementedOpcodeFault;
-
- this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
-
- this->cpu->hwrei();
-
- // FIXME: XXX check for interrupts? XXX
- return NoFault;
-}
-
-template <class Impl>
void
OzoneDynInst<Impl>::trap(Fault fault)
{
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b7fcf1708..b28a690bb 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -413,7 +413,6 @@ class BaseSimpleCPU : public BaseCPU
//Fault CacheOp(uint8_t Op, Addr EA);
#if FULL_SYSTEM
- Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
#else
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 377bfcd79..89d5ba99f 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -185,8 +185,6 @@ class SimpleThread : public ThreadState
void dumpFuncProfile();
- Fault hwrei();
-
bool simPalCheck(int palFunc);
#endif