diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:18 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:18 -0800 |
| commit | dc8018a5c3482008232e6faaa2d96cf20aed7485 (patch) | |
| tree | a972ac4544e227397595baf6eeb30e1854f480fc | |
| parent | c8c82f09a282832d919f7eb073a47be838e65b29 (diff) | |
| download | gem5-dc8018a5c3482008232e6faaa2d96cf20aed7485.tar.xz | |
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
90 files changed, 330 insertions, 330 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index b96a7011c..1a2c87828 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -1,6 +1,6 @@ # Copyright (c) 2012-2013, 2015 ARM Limited # All rights reserved -# +# # The license below extends only to copyright in the software and shall # not be construed as granting a license to any other intellectual # property including but not limited to intellectual property relating @@ -9,7 +9,7 @@ # terms below provided that you ensure that this notice is replicated # unmodified and in its entirety in all distributions of the software, # modified or unmodified, in source code or in binary form. -# +# # Copyright (c) 2010 Advanced Micro Devices, Inc. # All rights reserved. # diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 13edf601b..b18d65cbc 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -1,6 +1,6 @@ # Copyright (c) 2012-2013 ARM Limited # All rights reserved -# +# # The license below extends only to copyright in the software and shall # not be construed as granting a license to any other intellectual # property including but not limited to intellectual property relating diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py index e2887410f..b6e153be4 100644 --- a/configs/example/ruby_mem_test.py +++ b/configs/example/ruby_mem_test.py @@ -142,7 +142,7 @@ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, # artifical delay is randomly inserted on messages # system.ruby.randomization = True - + assert(len(cpus) == len(system.ruby._cpu_ports)) for (i, cpu) in enumerate(cpus): diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index a114afaea..d6de363a7 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -349,7 +349,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 0; i < 8; ++i) { uint8_t ra_ub = Ra_uq<hi:lo>; uint8_t rb_ub = Rb_uq<hi:lo>; - temp += (ra_ub >= rb_ub) ? + temp += (ra_ub >= rb_ub) ? (ra_ub - rb_ub) : (rb_ub - ra_ub); hi += 8; lo += 8; @@ -378,15 +378,15 @@ decode OPCODE default Unknown::unknown() { if (!(temp<7:0>)) { temp >>= 8; count += 8; } if (!(temp<3:0>)) { temp >>= 4; count += 4; } if (!(temp<1:0>)) { temp >>= 2; count += 2; } - if (!(temp<0:0> & ULL(0x1))) { - temp >>= 1; count += 1; + if (!(temp<0:0> & ULL(0x1))) { + temp >>= 1; count += 1; } if (!(temp<0:0> & ULL(0x1))) count += 1; Rc = count; }}, IntAluOp); - 0x34: unpkbw({{ + 0x34: unpkbw({{ Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 16) | (Rb_uq<23:16> << 32) @@ -415,7 +415,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 7; i >= 0; --i) { int8_t ra_sb = Ra_uq<hi:lo>; int8_t rb_sb = Rb_uq<hi:lo>; - temp = ((temp << 8) + temp = ((temp << 8) | ((ra_sb < rb_sb) ? Ra_uq<hi:lo> : Rb_uq<hi:lo>)); hi -= 8; @@ -431,7 +431,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 3; i >= 0; --i) { int16_t ra_sw = Ra_uq<hi:lo>; int16_t rb_sw = Rb_uq<hi:lo>; - temp = ((temp << 16) + temp = ((temp << 16) | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> : Rb_uq<hi:lo>)); hi -= 16; @@ -447,7 +447,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 7; i >= 0; --i) { uint8_t ra_ub = Ra_uq<hi:lo>; uint8_t rb_ub = Rb_uq<hi:lo>; - temp = ((temp << 8) + temp = ((temp << 8) | ((ra_ub < rb_ub) ? Ra_uq<hi:lo> : Rb_uq<hi:lo>)); hi -= 8; @@ -463,7 +463,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 3; i >= 0; --i) { uint16_t ra_sw = Ra_uq<hi:lo>; uint16_t rb_sw = Rb_uq<hi:lo>; - temp = ((temp << 16) + temp = ((temp << 16) | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> : Rb_uq<hi:lo>)); hi -= 16; @@ -479,7 +479,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 7; i >= 0; --i) { uint8_t ra_ub = Ra_uq<hi:lo>; uint8_t rb_ub = Rb_uq<hi:lo>; - temp = ((temp << 8) + temp = ((temp << 8) | ((ra_ub > rb_ub) ? Ra_uq<hi:lo> : Rb_uq<hi:lo>)); hi -= 8; @@ -495,7 +495,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 3; i >= 0; --i) { uint16_t ra_uw = Ra_uq<hi:lo>; uint16_t rb_uw = Rb_uq<hi:lo>; - temp = ((temp << 16) + temp = ((temp << 16) | ((ra_uw > rb_uw) ? Ra_uq<hi:lo> : Rb_uq<hi:lo>)); hi -= 16; @@ -511,7 +511,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 7; i >= 0; --i) { int8_t ra_sb = Ra_uq<hi:lo>; int8_t rb_sb = Rb_uq<hi:lo>; - temp = ((temp << 8) + temp = ((temp << 8) | ((ra_sb > rb_sb) ? Ra_uq<hi:lo> : Rb_uq<hi:lo>)); hi -= 8; @@ -527,7 +527,7 @@ decode OPCODE default Unknown::unknown() { for (int i = 3; i >= 0; --i) { int16_t ra_sw = Ra_uq<hi:lo>; int16_t rb_sw = Rb_uq<hi:lo>; - temp = ((temp << 16) + temp = ((temp << 16) | ((ra_sw > rb_sw) ? Ra_uq<hi:lo> : Rb_uq<hi:lo>)); hi -= 16; diff --git a/src/arch/alpha/linux/linux.hh b/src/arch/alpha/linux/linux.hh index 115508405..f019b4f21 100644 --- a/src/arch/alpha/linux/linux.hh +++ b/src/arch/alpha/linux/linux.hh @@ -127,7 +127,7 @@ class AlphaLinux : public Linux static const unsigned TGT_RLIMIT_AS = 7; static const unsigned TGT_RLIMIT_NOFILE = 6; static const unsigned TGT_RLIMIT_MEMLOCK = 9; - + typedef struct { int64_t uptime; /* Seconds since boot */ uint64_t loads[3]; /* 1, 5, and 15 minute load averages */ diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index e214c8874..3b37b42c7 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -75,7 +75,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize) ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); if(elfObject) { - // modern glibc uses a bunch of auxiliary vectors to set up + // modern glibc uses a bunch of auxiliary vectors to set up // TLS as well as do a bunch of other stuff // these vectors go on the bottom of the stack, below argc/argv/envp // pointers but above actual arg strings @@ -111,10 +111,10 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize) } int space_needed = - argv_array_size + - envp_array_size + + argv_array_size + + envp_array_size + auxv_array_size + - arg_data_size + + arg_data_size + env_data_size; if (space_needed < 32*1024) diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 5f0ed85db..3360b34c5 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -230,9 +230,9 @@ TLB::checkCacheability(RequestPtr &req, bool itb) req->setPaddr(req->getPaddr() & PAddrUncachedMask); } // We shouldn't be able to read from an uncachable address in Alpha as - // we don't have a ROM and we don't want to try to fetch from a device - // register as we destroy any data that is clear-on-read. - if (req->isUncacheable() && itb) + // we don't have a ROM and we don't want to try to fetch from a device + // register as we destroy any data that is clear-on-read. + if (req->isUncacheable() && itb) return std::make_shared<UnimpFault>( "CPU trying to fetch from uncached I/O"); diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index f6c8f3c44..1aab3dc1b 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -45,7 +45,7 @@ Import('*') if env['TARGET_ISA'] == 'arm': # Workaround for bug in SCons version > 0.97d20071212 -# Scons bug id: 2006 M5 Bug id: 308 +# Scons bug id: 2006 M5 Bug id: 308 Dir('isa/formats') Source('decoder.cc') Source('faults.cc') diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc index 6682b75a0..4f57ecc51 100644 --- a/src/arch/arm/interrupts.cc +++ b/src/arch/arm/interrupts.cc @@ -39,7 +39,7 @@ #include "arch/arm/interrupts.hh" #include "arch/arm/system.hh" - + ArmISA::Interrupts * ArmInterruptsParams::create() { diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa index fc4b97984..ba9a39efb 100644 --- a/src/arch/arm/isa/bitfields.isa +++ b/src/arch/arm/isa/bitfields.isa @@ -65,7 +65,7 @@ def bitfield OPCODE_18 opcode18; def bitfield OPCODE_15_12 opcode15_12; def bitfield OPCODE_15 opcode15; def bitfield MISC_OPCODE miscOpcode; -def bitfield OPC2 opc2; +def bitfield OPC2 opc2; def bitfield OPCODE_7 opcode7; def bitfield OPCODE_6 opcode6; def bitfield OPCODE_4 opcode4; diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index b9745e8ba..8d254f571 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -41,7 +41,7 @@ // Authors: Stephen Hines let {{ - + calcCcCode = ''' if (%(canOverflow)s){ cprintf("canOverflow: %%d\\n", Rd < resTemp); @@ -52,7 +52,7 @@ let {{ _iz = (resTemp == 0); _iv = %(ivValue)s; _ic = %(icValue)s; - + CondCodesNZ = (_in << 1) | (_iz); CondCodesC = _ic; CondCodesV = _iv; @@ -79,7 +79,7 @@ let {{ iv = 'CondCodesV' negBit = 63 elif flagtype == "overflow": - canOverflow = "true" + canOverflow = "true" icReg = icImm = iv = '0' elif flagtype == "add": icReg = icImm = 'findCarry(32, resTemp, Rn, op2)' @@ -94,12 +94,12 @@ let {{ icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)' icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)' iv = 'CondCodesV' - return (calcCcCode % {"icValue" : icReg, - "ivValue" : iv, + return (calcCcCode % {"icValue" : icReg, + "ivValue" : iv, "negBit" : negBit, "canOverflow" : canOverflow }, - calcCcCode % {"icValue" : icImm, - "ivValue" : iv, + calcCcCode % {"icValue" : icImm, + "ivValue" : iv, "negBit" : negBit, "canOverflow" : canOverflow }) @@ -116,7 +116,7 @@ let {{ negBit = 63 elif flagtype == "overflow": icVaule = ivValue = '0' - canOverflow = "true" + canOverflow = "true" elif flagtype == "add": icValue = 'findCarry(32, resTemp, Rn, rotated_imm)' ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)' diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh index 0dd1df373..dd2f1675d 100644 --- a/src/arch/arm/linux/linux.hh +++ b/src/arch/arm/linux/linux.hh @@ -177,7 +177,7 @@ class ArmLinux32 : public Linux uint32_t freehigh; /* Available high memory size */ uint32_t mem_unit; /* Memory unit size in bytes */ } tgt_sysinfo; - + /// For getrusage(). struct rusage { struct timeval ru_utime; //!< user time used diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc index 7cc650c58..0246ffd4e 100644 --- a/src/arch/arm/stacktrace.cc +++ b/src/arch/arm/stacktrace.cc @@ -170,7 +170,7 @@ namespace ArmISA StackTrace::dump() { DPRINTFN("------ Stack ------\n"); - + DPRINTFN(" Not implemented\n"); } #endif diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 52cbc4041..1f930f3f5 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -359,7 +359,7 @@ decode OPCODE_HI default Unknown::unknown() { Rt &= 0xFFFFE7FF; } }}); - 0x4: mtc0({{ + 0x4: mtc0({{ CP0_RD_SEL = Rt; CauseReg cause = Cause; IntCtlReg intCtl = IntCtl; @@ -1238,7 +1238,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x3: CP1Unimpl::unknown(); 0x7: CP1Unimpl::unknown(); - //Table A-16 MIPS32 COP1 Encoding of Function + //Table A-16 MIPS32 COP1 Encoding of Function //Field When rs=W 0x4: decode FUNCTION { format FloatConvertOp { @@ -1867,7 +1867,7 @@ decode OPCODE_HI default Unknown::unknown() { }}); 0x7: precr_sra_r_ph_w({{ Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, - SIMD_FMT_W, ROUND); + SIMD_FMT_W, ROUND); }}); } } diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh index 992bbf85d..38f958c89 100644 --- a/src/arch/mips/linux/linux.hh +++ b/src/arch/mips/linux/linux.hh @@ -125,7 +125,7 @@ class MipsLinux : public Linux /// assign themselves to process IDs reserved for /// the root users. static const int NUM_ROOT_PROCS = 2; - + typedef struct { int32_t uptime; /* Seconds since boot */ uint32_t loads[3]; /* 1, 5, and 15 minute load averages */ @@ -140,7 +140,7 @@ class MipsLinux : public Linux uint32_t freehigh; /* Available high memory size */ uint32_t mem_unit; /* Memory unit size in bytes */ } tgt_sysinfo; - + }; #endif diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index ef21179e5..c6c40188e 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -77,7 +77,7 @@ sys_getsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process, switch (op) { case 45: - { + { // GSI_IEEE_FP_CONTROL TypedBufferArg<uint64_t> fpcr(bufPtr); // I don't think this exactly matches the HW FPCR diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh index cc4e4a859..cb129fba7 100755 --- a/src/arch/mips/pagetable.hh +++ b/src/arch/mips/pagetable.hh @@ -65,7 +65,7 @@ struct PTE bool V1; // Odd entry Valid Bit uint8_t C1; // Cache Coherency Bits (3 bits) - /* + /* * The next few variables are put in as optimizations to reduce * TLB lookup overheads. For a given Mask, what is the address shift * amount, and what is the OffsetMask diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript index c49fab649..e26035cbe 100644 --- a/src/arch/power/SConscript +++ b/src/arch/power/SConscript @@ -32,7 +32,7 @@ Import('*') if env['TARGET_ISA'] == 'power': # Workaround for bug in SCons version > 0.97d20071212 -# Scons bug id: 2006 M5 Bug id: 308 +# Scons bug id: 2006 M5 Bug id: 308 Dir('isa/formats') Source('decoder.cc') Source('insts/branch.cc') diff --git a/src/arch/sparc/interrupts.cc b/src/arch/sparc/interrupts.cc index 96d61e559..1891361d5 100644 --- a/src/arch/sparc/interrupts.cc +++ b/src/arch/sparc/interrupts.cc @@ -29,7 +29,7 @@ */ #include "arch/sparc/interrupts.hh" - + SparcISA::Interrupts * SparcInterruptsParams::create() { diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh index bb7063edf..bbedc92b1 100644 --- a/src/arch/sparc/linux/linux.hh +++ b/src/arch/sparc/linux/linux.hh @@ -78,8 +78,8 @@ class SparcLinux : public Linux static const unsigned TGT_MAP_ANONYMOUS = 0x20; static const unsigned TGT_MAP_FIXED = 0x10; - - typedef struct { + + typedef struct { int64_t uptime; /* Seconds since boot */ uint64_t loads[3]; /* 1, 5, and 15 minute load averages */ uint64_t totalram; /* Total usable main memory size */ @@ -151,7 +151,7 @@ class Sparc32Linux : public SparcLinux uint32_t __unused4; uint32_t __unused5; } tgt_stat64; - + typedef struct { int32_t uptime; /* Seconds since boot */ uint32_t loads[3]; /* 1, 5, and 15 minute load averages */ @@ -165,7 +165,7 @@ class Sparc32Linux : public SparcLinux uint32_t totalhigh; /* Total high memory size */ uint32_t freehigh; /* Available high memory size */ uint32_t mem_unit; /* Memory unit size in bytes */ - } tgt_sysinfo; + } tgt_sysinfo; /// Resource constants for getrlimit() (overide some generics). static const unsigned TGT_RLIMIT_NPROC = 7; diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh index 79b4d3cc5..20df5a653 100644 --- a/src/arch/sparc/pagetable.hh +++ b/src/arch/sparc/pagetable.hh @@ -57,7 +57,7 @@ class TteTag TteTag(uint64_t e) : entry(e), populated(true) {} const TteTag & - operator=(uint64_t e) + operator=(uint64_t e) { populated = true; entry = e; diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc index e15dcd331..6817ca742 100644 --- a/src/arch/x86/cpuid.cc +++ b/src/arch/x86/cpuid.cc @@ -49,7 +49,7 @@ namespace X86ISA { L2L3CacheAndL2TLB, APMInfo, LongModeAddressSize, - + /* * The following are defined by the spec but not yet implemented */ diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc index b7d9335d4..7724c0217 100644 --- a/src/arch/x86/faults.cc +++ b/src/arch/x86/faults.cc @@ -103,7 +103,7 @@ namespace X86ISA return ss.str(); } - + void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst) { X86FaultBase::invoke(tc); diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh index cedd16820..1259b6982 100644 --- a/src/arch/x86/insts/micromediaop.hh +++ b/src/arch/x86/insts/micromediaop.hh @@ -68,7 +68,7 @@ namespace X86ISA { return ext & MediaScalarOp; } - + int numItems(int size) const { diff --git a/src/arch/x86/isa/insts/general_purpose/system_calls.py b/src/arch/x86/isa/insts/general_purpose/system_calls.py index d6f1a39bf..59519c0ae 100644 --- a/src/arch/x86/isa/insts/general_purpose/system_calls.py +++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py @@ -43,7 +43,7 @@ def macroop SYSCALL_64 # Save the next RIP. rdip rcx - + # Stick rflags with RF masked into r11. rflags t2 limm t3, "~RFBit", dataSize=8 @@ -96,7 +96,7 @@ def macroop SYSCALL_COMPAT # Save the next RIP. rdip rcx - + # Stick rflags with RF masked into r11. rflags t2 limm t3, "~RFBit", dataSize=8 diff --git a/src/arch/x86/isa/insts/romutil.py b/src/arch/x86/isa/insts/romutil.py index 10653e1cc..ed43171bb 100644 --- a/src/arch/x86/isa/insts/romutil.py +++ b/src/arch/x86/isa/insts/romutil.py @@ -66,7 +66,7 @@ def rom wrdh t9, t4, t2, dataSize=8 - # + # # Figure out where the stack should be # @@ -74,7 +74,7 @@ def rom rdsel t11, ss # Check if we're changing privelege level. At this point we can assume - # we're going to a DPL that's less than or equal to the CPL. + # we're going to a DPL that's less than or equal to the CPL. rdattr t10, hs, dataSize=8 andi t10, t10, 3, dataSize=8 rdattr t5, cs, dataSize=8 @@ -139,7 +139,7 @@ def rom # Build up the interrupt stack frame # - + # Write out the contents of memory %(errorCodeCode)s st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8 @@ -173,7 +173,7 @@ def rom # Put the results into rflags wrflags t6, t10 - + eret }; ''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py index 027747b52..c3df35708 100644 --- a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py +++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py @@ -50,7 +50,7 @@ def macroop MOVD_MMX_P { }; def macroop MOVD_R_MMX { - mov2int reg, mmxm, size=dsz + mov2int reg, mmxm, size=dsz }; def macroop MOVD_M_MMX { diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index 5798ac4b0..dc36d0edb 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -51,7 +51,7 @@ let {{ let {{ class X86Microop(object): - + generatorNameTemplate = "generate_%s_%d" generatorTemplate = ''' diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index e5f04109f..cdb3b4899 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -214,7 +214,7 @@ let {{ if ext is None: self.ext = 0 else: - self.ext = ext + self.ext = ext def getAllocator(self, microFlags): className = self.className @@ -926,7 +926,7 @@ let {{ uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex); uint64_t resBits = arg1Bits + arg2Bits; - + if (ext & 0x2) { if (signedOp()) { int arg1Sign = bits(arg1Bits, sizeBits - 1); @@ -963,7 +963,7 @@ let {{ uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex); uint64_t resBits = arg1Bits - arg2Bits; - + if (ext & 0x2) { if (signedOp()) { int arg1Sign = bits(arg1Bits, sizeBits - 1); @@ -1025,7 +1025,7 @@ let {{ if (ext & 0x4) resBits += (ULL(1) << (destBits - 1)); - + if (multHi()) resBits >>= destBits; @@ -1050,7 +1050,7 @@ let {{ uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex); uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2; - + result = insertBits(result, hiIndex, loIndex, resBits); } FpDestReg_uqw = result; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 15515ed12..ef0c4cb18 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -238,7 +238,7 @@ let {{ global exec_output # Stick all the code together so it can be searched at once - allCode = "|".join((code, flag_code, cond_check, else_code, + allCode = "|".join((code, flag_code, cond_check, else_code, cond_control_flag_init)) allBigCode = "|".join((big_code, flag_code, cond_check, else_code, cond_control_flag_init)) @@ -786,7 +786,7 @@ let {{ PredecfBit = PredecfBit & ~(ext & ECFBit); //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && + if ((ext & (CFBit | ECFBit)) && shiftAmt <= dataSize * 8 && bits(SrcReg1, shiftAmt - 1)) { PredcfofBits = PredcfofBits | (ext & CFBit); @@ -1018,7 +1018,7 @@ let {{ int msb = bits(DestReg, dataSize * 8 - 1); int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && + if ((ext & (CFBit | ECFBit)) && (realShiftAmt == 0) ? origCFBit : CFBits) { PredcfofBits = PredcfofBits | (ext & CFBit); PredecfBit = PredecfBit | (ext & ECFBit); diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 5a00ce78c..0e3cff937 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -612,7 +612,7 @@ I386LiveProcess::initState() argsInit(sizeof(uint32_t), PageBytes); - /* + /* * Set up a GDT for this process. The whole GDT wouldn't really be for * this process, but the only parts we care about are. */ diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh index 2fb051953..ab513d839 100644 --- a/src/arch/x86/process.hh +++ b/src/arch/x86/process.hh @@ -74,7 +74,7 @@ namespace X86ISA public: Addr gdtStart() { return _gdtStart; } - + Addr gdtSize() { return _gdtSize; } diff --git a/src/base/cp_annotate.cc b/src/base/cp_annotate.cc index 5c421a5cf..70ab31167 100644 --- a/src/base/cp_annotate.cc +++ b/src/base/cp_annotate.cc @@ -180,8 +180,8 @@ CPA::swSmBegin(ThreadContext *tc) int smi = getSm(sysi, sm, args[1]); DPRINTF(Annotate, "Starting machine: %s(%d) sysi: %d id: %#x\n", sm, smi, sysi, args[1]); - DPRINTF(Annotate, "smMap[%d] = %d, %s, %#x\n", smi, - smMap[smi-1].first, smMap[smi-1].second.first, + DPRINTF(Annotate, "smMap[%d] = %d, %s, %#x\n", smi, + smMap[smi-1].first, smMap[smi-1].second.first, smMap[smi-1].second.second); uint64_t frame = getFrame(tc); @@ -226,7 +226,7 @@ CPA::swSmBegin(ThreadContext *tc) scLinks[sysi-1].erase(id); an->stq = smi; an->dump = true; - DPRINTF(Annotate, + DPRINTF(Annotate, "Found prev unknown linking from %d to state machine %s(%d)\n", an->sm, sm, smi); @@ -288,11 +288,11 @@ CPA::doSwSmEnd(System *sys, int cpuid, string sm, uint64_t frame) warn("State machine stack not unwinding correctly at %d\n", curTick()); } else { - DPRINTF(Annotate, + DPRINTF(Annotate, "State machine ending:%s sysi:%d id:%#x back:%d getSm:%d\n", sm, sysi, smMap[smib-1].second.second, smStack[sid].back(), getSm(sysi, sm, smMap[smib-1].second.second)); - assert(getSm(sysi, sm, smMap[smib-1].second.second) == + assert(getSm(sysi, sm, smMap[smib-1].second.second) == smStack[sid].back()); int smi = smStack[sid].back(); @@ -400,7 +400,7 @@ CPA::swEnd(ThreadContext *tc) tc->readIntReg(ReturnAddressReg), st, junk); System *sys = tc->getSystemPtr(); StringWrap name(sys->name()); - + int sysi = getSys(sys); StackId sid = StackId(sysi, getFrame(tc)); if (!smStack[sid].size()) { @@ -443,7 +443,7 @@ CPA::swQ(ThreadContext *tc) //warn("Tried to queue 0 bytes in %s, ignoring\n", q); return; } - DPRINTFS(AnnotateQ, sys, + DPRINTFS(AnnotateQ, sys, "swQ: %s[%#x] cur size %d %d bytes: %d adding: %d\n", q, id, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count); doQ(sys, FL_NONE, tc->contextId(), smi, q, qi, count); @@ -470,7 +470,7 @@ CPA::swDq(ThreadContext *tc) int qi = getQ(sysi, q, id); if (swExpl[sid]) swExpl[sid] = false; - DPRINTFS(AnnotateQ, sys, + DPRINTFS(AnnotateQ, sys, "swDq: %s[%#x] cur size %d %d bytes: %d removing: %d\n", q, id, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count); assert(count != 0); @@ -499,7 +499,7 @@ CPA::swPq(ThreadContext *tc) int qi = getQ(sysi, q, id); if (swExpl[sid]) swExpl[sid] = false; - DPRINTFS(AnnotateQ, sys, + DPRINTFS(AnnotateQ, sys, "swPq: %s [%#x] cur size %d %d bytes: %d peeking: %d\n", q, id, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count); @@ -534,7 +534,7 @@ CPA::swRq(ThreadContext *tc) int qi = getQ(sysi, q, id); if (swExpl[sid]) swExpl[sid] = false; - DPRINTFS(AnnotateQ, sys, + DPRINTFS(AnnotateQ, sys, "swRq: %s [%#x] cur size %d %d bytes: %d reserve: %d\n", q, id, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count); @@ -696,7 +696,7 @@ CPA::swAq(ThreadContext *tc) x++; } - warn("%d: Queue Assert: SW said there should be %d byte(s) in %s," + warn("%d: Queue Assert: SW said there should be %d byte(s) in %s," "however there are %d byte(s)\n", curTick(), size, q, qBytes[qi-1]); DPRINTF(AnnotateQ, "%d: Queue Assert: SW said there should be %d" @@ -805,7 +805,7 @@ CPA::swSyscallLink(ThreadContext *tc) smi, lsm); if (scLinks[sysi-1][id]) - DPRINTF(Annotate, + DPRINTF(Annotate, "scLinks already contains entry for system %d %s[%x] of %d\n", sysi, lsm, getFrame(tc), scLinks[sysi-1][id]); assert(scLinks[sysi-1][id] == 0); @@ -837,7 +837,7 @@ CPA::add(int t, int f, int c, int sm, int stq, int32_t d) DPRINTF(AnnotateVerbose, "Annotate: op: %d flags: 0x%x sm: %d state: %d time: %d, data: %d\n", an->op, an->flag, an->sm, an->stq, an->time, an->data); - + // Don't dump Links because we might be setting no-dump on it if (an->op != OP_LINK) dump(false); diff --git a/src/base/cp_annotate.hh b/src/base/cp_annotate.hh index 0a0cc34a3..587ea0f1a 100644 --- a/src/base/cp_annotate.hh +++ b/src/base/cp_annotate.hh @@ -101,25 +101,25 @@ class CPA void swIdentify(ThreadContext *tc) { return; } uint64_t swGetId(ThreadContext *tc) { return 0; } void swSyscallLink(ThreadContext *tc) { return; } - void hwBegin(flags f, System *sys, uint64_t frame, std::string sm, + void hwBegin(flags f, System *sys, uint64_t frame, std::string sm, std::string st) { return; } - void hwQ(flags f, System *sys, uint64_t frame, std::string sm, - std::string q, uint64_t qid, System *q_sys = NULL, + void hwQ(flags f, System *sys, uint64_t frame, std::string sm, + std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { return; } - void hwDq(flags f, System *sys, uint64_t frame, std::string sm, - std::string q, uint64_t qid, System *q_sys = NULL, + void hwDq(flags f, System *sys, uint64_t frame, std::string sm, + std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { return; } - void hwPq(flags f, System *sys, uint64_t frame, std::string sm, - std::string q, uint64_t qid, System *q_sys = NULL, + void hwPq(flags f, System *sys, uint64_t frame, std::string sm, + std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { return; } - void hwRq(flags f, System *sys, uint64_t frame, std::string sm, - std::string q, uint64_t qid, System *q_sys = NULL, + void hwRq(flags f, System *sys, uint64_t frame, std::string sm, + std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { return; } - void hwWf(flags f, System *sys, uint64_t frame, std::string sm, - std::string q, uint64_t qid, System *q_sys = NULL, + void hwWf(flags f, System *sys, uint64_t frame, std::string sm, + std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { return; } - void hwWe(flags f, System *sys, uint64_t frame, std::string sm, - std::string q, uint64_t qid, System *q_sys = NULL, + void hwWe(flags f, System *sys, uint64_t frame, std::string sm, + std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { return; } }; #else @@ -145,7 +145,7 @@ class CPA : SimObject { public: typedef CPAParams Params; - + /** The known operations that are written to the annotation output file. */ enum ops { OP_BEGIN = 0x01, @@ -171,7 +171,7 @@ class CPA : SimObject /* Queue like a stack, not a queue */ FL_QOPP = 0x04, /* Mark HW state as waiting for some non-resource constraint - * (e.g. wait because SM only starts after 10 items are queued) */ + * (e.g. wait because SM only starts after 10 items are queued) */ FL_WAIT = 0x08, /* operation is linking to another state machine */ FL_LINK = 0x10, @@ -222,9 +222,9 @@ class CPA : SimObject std::vector<uint64_t> annotateIdx; - // number of state machines encountered in the simulation + // number of state machines encountered in the simulation int numSm; - // number of states encountered in the simulation + // number of states encountered in the simulation int numSmt; // number of states/queues for a given state machine/system respectively std::vector<int> numSt, numQ; @@ -291,7 +291,7 @@ class CPA : SimObject NameCache nameCache; // Stack of state machines currently nested (should unwind correctly) SmStack smStack; - // Map of currently outstanding links + // Map of currently outstanding links LinkMap lnMap; // If the state machine is currently exculding automatic changes SwExpl swExpl; @@ -299,7 +299,7 @@ class CPA : SimObject IMap lastState; // Hold mapping of sm and queues to output python IdMap smMap, qMap; - // Items still in queue, used for sanity checking + // Items still in queue, used for sanity checking std::vector<AnnotateList> qData; void doDq(System *sys, int flags, int cpu, int sm, std::string q, int qi, @@ -311,7 +311,7 @@ class CPA : SimObject // Turn a system id, state machine string, state machine id into a small int // for annotation output - int + int getSm(int sysi, std::string si, uint64_t id) { int smi; @@ -328,7 +328,7 @@ class CPA : SimObject // Turn a state machine string, state string into a small int // for annotation output - int + int getSt(std::string sm, std::string s) { int sti, smi; @@ -351,7 +351,7 @@ class CPA : SimObject } // Turn state machine pointer into a smal int for annotation output - int + int getSys(System *s) { NameCache::iterator i = nameCache.find(s); @@ -369,9 +369,9 @@ class CPA : SimObject return i->second.second; } - // Turn queue name, and queue context into small int for + // Turn queue name, and queue context into small int for // annotation output - int + int getQ(int sys, std::string q, uint64_t id) { int qi; @@ -390,7 +390,7 @@ class CPA : SimObject return qi; } - void swBegin(System *sys, int cpuid, std::string st, uint64_t frame, + void swBegin(System *sys, int cpuid, std::string st, uint64_t frame, bool expl = false, int flags = FL_NONE); AnnDataPtr add(int t, int f, int c, int sm, int stq, int32_t data=0); @@ -399,7 +399,7 @@ class CPA : SimObject bool _enabled; - /** Only allow one CPA object in a system. It doesn't make sense to have + /** Only allow one CPA object in a system. It doesn't make sense to have * more that one per simulation because if a part of the system was * important it would have annotations and queues, and with more than one * object none of the sanity checking for queues will work. */ @@ -429,7 +429,7 @@ class CPA : SimObject uint64_t swGetId(ThreadContext *tc); void swSyscallLink(ThreadContext *tc); - inline void hwBegin(flags f, System *sys, uint64_t frame, std::string sm, + inline void hwBegin(flags f, System *sys, uint64_t frame, std::string sm, std::string st) { if (!enabled()) @@ -442,7 +442,7 @@ class CPA : SimObject warn("BAD state encountered: at cycle %d: %s\n", curTick(), st); } - inline void hwQ(flags f, System *sys, uint64_t frame, std::string sm, + inline void hwQ(flags f, System *sys, uint64_t frame, std::string sm, std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { if (!enabled()) @@ -450,14 +450,14 @@ class CPA : SimObject int sysi = getSys(sys); int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid); - DPRINTFS(AnnotateQ, sys, + DPRINTFS(AnnotateQ, sys, "hwQ: %s[%#x] cur size %d %d bytes: %d adding: %d\n", q, qid, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count); doQ(sys, FL_HW | f, 0, getSm(sysi, sm, frame), q, qi, count); } - inline void hwDq(flags f, System *sys, uint64_t frame, std::string sm, + inline void hwDq(flags f, System *sys, uint64_t frame, std::string sm, std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { if (!enabled()) @@ -465,13 +465,13 @@ class CPA : SimObject int sysi = getSys(sys); int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid); - DPRINTFS(AnnotateQ, sys, + DPRINTFS(AnnotateQ, sys, "hwDQ: %s[%#x] cur size %d %d bytes: %d removing: %d\n", q, qid, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count); doDq(sys, FL_HW | f, 0, getSm(sysi,sm, frame), q, qi, count); } - inline void hwPq(flags f, System *sys, uint64_t frame, std::string sm, + inline void hwPq(flags f, System *sys, uint64_t frame, std::string sm, std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { if (!enabled()) @@ -479,13 +479,13 @@ class CPA : SimObject int sysi = getSys(sys); int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid); - DPRINTFS(AnnotateQ, sys, + DPRINTFS(AnnotateQ, sys, "hwPQ: %s[%#x] cur size %d %d bytes: %d peeking: %d\n", q, qid, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count); add(OP_PEEK, FL_HW | f, 0, getSm(sysi, sm, frame), qi, count); } - inline void hwRq(flags f, System *sys, uint64_t frame, std::string sm, + inline void hwRq(flags f, System *sys, uint64_t frame, std::string sm, std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { if (!enabled()) @@ -493,13 +493,13 @@ class CPA : SimObject int sysi = getSys(sys); int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid); - DPRINTFS(AnnotateQ, sys, + DPRINTFS(AnnotateQ, sys, "hwRQ: %s[%#x] cur size %d %d bytes: %d reserving: %d\n", q, qid, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count); add(OP_RESERVE, FL_HW | f, 0, getSm(sysi, sm, frame), qi, count); } - inline void hwWf(flags f, System *sys, uint64_t frame, std::string sm, + inline void hwWf(flags f, System *sys, uint64_t frame, std::string sm, std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { if (!enabled()) @@ -510,8 +510,8 @@ class CPA : SimObject add(OP_WAIT_FULL, FL_HW | f, 0, getSm(sysi, sm, frame), qi, count); } - inline void hwWe(flags f, System *sys, uint64_t frame, std::string sm, - std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) + inline void hwWe(flags f, System *sys, uint64_t frame, std::string sm, + std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1) { if (!enabled()) return; @@ -529,14 +529,14 @@ class CPA : SimObject static bool available() { return true; } - bool - enabled() - { + bool + enabled() + { if (!this) return false; return _enabled; } - + void dump(bool all); void dumpKey(); diff --git a/src/base/cprintf.hh b/src/base/cprintf.hh index 94a74728d..14b663c9c 100644 --- a/src/base/cprintf.hh +++ b/src/base/cprintf.hh @@ -69,7 +69,7 @@ struct Print { return data; } - + template <typename T> int get_number(const T& data) @@ -90,7 +90,7 @@ struct Print fmt.width = get_number(data); return; } - + if (fmt.get_precision) { fmt.get_precision = false; cont = true; diff --git a/src/base/flags.hh b/src/base/flags.hh index 2e0506391..caf23492a 100644 --- a/src/base/flags.hh +++ b/src/base/flags.hh @@ -44,7 +44,7 @@ class Flags operator const Type() const { return _flags; } - template <typename U> + template <typename U> const Flags<T> & operator=(const Flags<U> &flags) { @@ -58,7 +58,7 @@ class Flags _flags = flags; return *this; } - + bool isSet() const { return _flags; } bool isSet(Type flags) const { return (_flags & flags); } bool allSet() const { return !(~_flags); } diff --git a/src/base/inet.cc b/src/base/inet.cc index 190a7a11e..866b77fcf 100644 --- a/src/base/inet.cc +++ b/src/base/inet.cc @@ -374,7 +374,7 @@ TcpHdr::options(vector<const TcpOpt *> &vec) const return true; } -int +int hsplit(const EthPacketPtr &ptr) { int split_point = 0; diff --git a/src/base/inet.hh b/src/base/inet.hh index d7e003970..7d1235cc5 100644 --- a/src/base/inet.hh +++ b/src/base/inet.hh @@ -521,7 +521,7 @@ struct TcpHdr : public tcp_hdr void sum(uint16_t sum) { th_sum = sum; } void seq(uint32_t _seq) { th_seq = htonl(_seq); } - void flags(uint8_t _flags) { th_flags = _flags; } + void flags(uint8_t _flags) { th_flags = _flags; } bool options(std::vector<const TcpOpt *> &vec) const; diff --git a/src/base/loader/ecoff_object.cc b/src/base/loader/ecoff_object.cc index 3b9f6ba3f..c3c1c1108 100644 --- a/src/base/loader/ecoff_object.cc +++ b/src/base/loader/ecoff_object.cc @@ -39,7 +39,7 @@ // Only alpha will be able to load ecoff files for now. // base/types.hh and ecoff_machdep.h must be before the other .h files -// because they are are gathered from other code bases and require some +// because they are are gathered from other code bases and require some // typedefs from those files. #include "arch/alpha/ecoff_machdep.h" #include "base/loader/coff_sym.h" diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index d1d89f20b..c9684c42a 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -347,7 +347,7 @@ ElfObject::ElfObject(const string &_filename, size_t _len, uint8_t *_data, data.size = phdr.p_filesz; data.fileImage = fileData + phdr.p_offset; } else { - // If it's none of the above but is loadable, + // If it's none of the above but is loadable, // load the filesize worth of data Segment extra; extra.baseAddr = phdr.p_paddr; diff --git a/src/base/statistics.cc b/src/base/statistics.cc index b63e69b68..131c74566 100644 --- a/src/base/statistics.cc +++ b/src/base/statistics.cc @@ -178,7 +178,7 @@ Info::setName(const string &name) Info *other = p.first->second; bool result = p.second; - + if (!result) { // using other->name instead of just name to avoid a compiler // warning. They should be the same. diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index 93d04a8f7..4ff82da8e 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -1,4 +1,4 @@ -/* +/* * Copyright (c) 2012, 2014 ARM Limited * All rights reserved * diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 441d5f896..97a280b17 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -817,7 +817,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) delete pkt; PacketPtr big_pkt = send_state->bigPkt; delete send_state; - + SplitMainSenderState * main_send_state = dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); assert(main_send_state); @@ -932,7 +932,7 @@ TimingSimpleCPU::DcachePort::recvReqRetry() dynamic_cast<SplitFragmentSenderState *>(tmp->senderState); assert(send_state); PacketPtr big_pkt = send_state->bigPkt; - + SplitMainSenderState * main_send_state = dynamic_cast<SplitMainSenderState *>(big_pkt->senderState); assert(main_send_state); diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc b/src/cpu/testers/directedtest/DirectedGenerator.cc index d69261cf0..5aee2a91c 100644 --- a/src/cpu/testers/directedtest/DirectedGenerator.cc +++ b/src/cpu/testers/directedtest/DirectedGenerator.cc @@ -38,7 +38,7 @@ DirectedGenerator::DirectedGenerator(const Params *p) m_directed_tester = NULL; } -void +void DirectedGenerator::setDirectedTester(RubyDirectedTester* directed_tester) { assert(m_directed_tester == NULL); diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh index 422a0ddb6..2d033723d 100644 --- a/src/cpu/testers/directedtest/DirectedGenerator.hh +++ b/src/cpu/testers/directedtest/DirectedGenerator.hh @@ -34,19 +34,19 @@ #include "params/DirectedGenerator.hh" #include "sim/sim_object.hh" -class DirectedGenerator : public SimObject +class DirectedGenerator : public SimObject { public: typedef DirectedGeneratorParams Params; DirectedGenerator(const Params *p); - + virtual ~DirectedGenerator() {} - + virtual bool initiate() = 0; virtual void performCallback(uint32_t proc, Addr address) = 0; - + void setDirectedTester(RubyDirectedTester* directed_tester); - + protected: int m_num_cpus; MasterID masterId; diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc index 61c3f5972..6f4877309 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.cc +++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc @@ -98,10 +98,10 @@ InvalidateGenerator::initiate() } } -void +void InvalidateGenerator::performCallback(uint32_t proc, Addr address) { - assert(m_address == address); + assert(m_address == address); if (m_status == InvalidateGeneratorStatus_Load_Pending) { assert(m_active_read_node == proc); @@ -128,8 +128,8 @@ InvalidateGenerator::performCallback(uint32_t proc, Addr address) // m_directed_tester->incrementCycleCompletions(); m_status = InvalidateGeneratorStatus_Load_Waiting; - } - + } + } InvalidateGenerator * diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.hh b/src/cpu/testers/directedtest/InvalidateGenerator.hh index 50db180e3..0e842bd3f 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.hh +++ b/src/cpu/testers/directedtest/InvalidateGenerator.hh @@ -27,7 +27,7 @@ */ // -// This Directed Generator generates GETX requests for all nodes in the +// This Directed Generator generates GETX requests for all nodes in the // system. The GETX requests are generated one at a time in round-robin fashion // 0...1...2...etc. // @@ -40,17 +40,17 @@ #include "mem/protocol/InvalidateGeneratorStatus.hh" #include "params/InvalidateGenerator.hh" -class InvalidateGenerator : public DirectedGenerator +class InvalidateGenerator : public DirectedGenerator { public: typedef InvalidateGeneratorParams Params; InvalidateGenerator(const Params *p); - + ~InvalidateGenerator(); - + bool initiate(); void performCallback(uint32_t proc, Addr address); - + private: InvalidateGeneratorStatus m_status; Addr m_address; diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc index 70da23f03..b85031720 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -93,7 +93,7 @@ bool RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt) { tester->hitCallback(id, pkt->getAddr()); - + // // Now that the tester has completed, delete the packet, then return // @@ -118,7 +118,7 @@ RubyDirectedTester::hitCallback(NodeID proc, Addr addr) proc, addr); - generator->performCallback(proc, addr); + generator->performCallback(proc, addr); schedule(directedStartEvent, curTick()); } diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc index 2356fb47a..62d03fbf6 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc @@ -87,11 +87,11 @@ SeriesRequestGenerator::initiate() } } -void +void SeriesRequestGenerator::performCallback(uint32_t proc, Addr address) { assert(m_active_node == proc); - assert(m_address == address); + assert(m_address == address); assert(m_status == SeriesRequestGeneratorStatus_Request_Pending); m_status = SeriesRequestGeneratorStatus_Thinking; diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh index 944a179cb..8c64a3dd0 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh @@ -27,7 +27,7 @@ */ // -// This Deterministic Generator generates GETX requests for all nodes in the +// This Deterministic Generator generates GETX requests for all nodes in the // system. The GETX requests are generated one at a time in round-robin fashion // 0...1...2...etc. // @@ -40,17 +40,17 @@ #include "mem/protocol/SeriesRequestGeneratorStatus.hh" #include "params/SeriesRequestGenerator.hh" -class SeriesRequestGenerator : public DirectedGenerator +class SeriesRequestGenerator : public DirectedGenerator { public: typedef SeriesRequestGeneratorParams Params; SeriesRequestGenerator(const Params *p); - + ~SeriesRequestGenerator(); - + bool initiate(); void performCallback(uint32_t proc, Addr address); - + private: SeriesRequestGeneratorStatus m_status; Addr m_address; diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc index e3103f6b6..79a563f28 100644 --- a/src/cpu/testers/networktest/networktest.cc +++ b/src/cpu/testers/networktest/networktest.cc @@ -207,14 +207,14 @@ NetworkTest::generatePkt() // Modeling different coherence msg types over different msg classes. // - // networktest assumes the Network_test coherence protocol + // networktest assumes the Network_test coherence protocol // which models three message classes/virtual networks. // These are: request, forward, response. // requests and forwards are "control" packets (typically 8 bytes), // while responses are "data" packets (typically 72 bytes). // // Life of a packet from the tester into the network: - // (1) This function generatePkt() generates packets of one of the + // (1) This function generatePkt() generates packets of one of the // following 3 types (randomly) : ReadReq, INST_FETCH, WriteReq // (2) mem/ruby/system/RubyPort.cc converts these to RubyRequestType_LD, // RubyRequestType_IFETCH, RubyRequestType_ST respectively @@ -222,13 +222,13 @@ NetworkTest::generatePkt() // in the coherence protocol. // (4) Network_test-cache.sm tags RubyRequestType:LD, // RubyRequestType:IFETCH and RubyRequestType:ST as - // Request, Forward, and Response events respectively; + // Request, Forward, and Response events respectively; // and injects them into virtual networks 0, 1 and 2 respectively. // It immediately calls back the sequencer. // (5) The packet traverses the network (simple/garnet) and reaches its // destination (Directory), and network stats are updated. // (6) Network_test-dir.sm simply drops the packet. - // + // MemCmd::Command requestType; Request *req = nullptr; diff --git a/src/cpu/timebuf.hh b/src/cpu/timebuf.hh index e93fe0e79..2cd965c04 100644 --- a/src/cpu/timebuf.hh +++ b/src/cpu/timebuf.hh @@ -138,7 +138,7 @@ class TimeBuffer public: TimeBuffer(int p, int f) - : past(p), future(f), size(past + future + 1), + : past(p), future(f), size(past + future + 1), data(new char[size * sizeof(T)]), index(size), base(0) { assert(past >= 0 && future >= 0); diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc index 02c302bae..1eaaf96a2 100644 --- a/src/dev/mc146818.cc +++ b/src/dev/mc146818.cc @@ -275,7 +275,7 @@ MC146818::serialize(const string &base, CheckpointOut &cp) const paramOut(cp, base + ".stat_regB", (uint8_t)regB_serial); // - // save the timer tick and rtc clock tick values to correctly reschedule + // save the timer tick and rtc clock tick values to correctly reschedule // them during unserialize // Tick rtcTimerInterruptTickOffset = event.when() - curTick(); diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc index cba773f39..d299dad42 100644 --- a/src/dev/net/i8254xGBe.cc +++ b/src/dev/net/i8254xGBe.cc @@ -61,9 +61,9 @@ IGbE::IGbE(const Params *p) : EtherDevice(p), etherInt(NULL), cpa(NULL), rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false), txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0), - fetchDelay(p->fetch_delay), wbDelay(p->wb_delay), - fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay), - rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay), + fetchDelay(p->fetch_delay), wbDelay(p->wb_delay), + fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay), + rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay), rdtrEvent(this), radvEvent(this), tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this), rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size), @@ -867,7 +867,7 @@ IGbE::DescCache<T>::writeback(Addr aMask) moreToWb = false; wbAlignment = aMask; - + DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: " "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n", @@ -895,11 +895,11 @@ IGbE::DescCache<T>::writeback(Addr aMask) wbOut = max_to_wb; - assert(!wbDelayEvent.scheduled()); + assert(!wbDelayEvent.scheduled()); igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay); igbe->anBegin(annSmWb, "Prepare Writeback Desc"); } - + template<class T> void IGbE::DescCache<T>::writeback1() @@ -911,7 +911,7 @@ IGbE::DescCache<T>::writeback1() } DPRINTF(EthernetDesc, "Begining DMA of %d descriptors\n", wbOut); - + for (int x = 0; x < wbOut; x++) { assert(usedCache.size()); memcpy(&wbBuf[x], usedCache[x], sizeof(T)); @@ -920,7 +920,7 @@ IGbE::DescCache<T>::writeback1() igbe->anQ(annSmWb, annUsedDescQ); } - + igbe->anBegin(annSmWb, "Writeback Desc DMA"); assert(wbOut); @@ -962,7 +962,7 @@ IGbE::DescCache<T>::fetchDescriptors() } max_to_fetch = std::min(max_to_fetch, free_cache); - + DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: " "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n", @@ -972,7 +972,7 @@ IGbE::DescCache<T>::fetchDescriptors() // Nothing to do if (max_to_fetch == 0) return; - + // So we don't have two descriptor fetches going on at once curFetching = max_to_fetch; @@ -1058,7 +1058,7 @@ IGbE::DescCache<T>::wbComplete() #ifndef NDEBUG long oldHead = curHead; #endif - + for (int x = 0; x < wbOut; x++) { assert(usedCache.size()); delete usedCache[0]; @@ -1192,7 +1192,7 @@ IGbE::DescCache<T>::unserialize(CheckpointIn &cp) ///////////////////////////// IGbE::RxDescCache ////////////////////////////// IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s) - : DescCache<RxDesc>(i, n, s), pktDone(false), splitCount(0), + : DescCache<RxDesc>(i, n, s), pktDone(false), splitCount(0), pktEvent(this), pktHdrEvent(this), pktDataEvent(this) { @@ -1260,10 +1260,10 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet, int pkt_offset) break; case RXDT_ADV_SPLIT_A: int split_point; - + buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() : igbe->regs.rctl.descSize(); - hdr_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.hdrLen() : 0; + hdr_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.hdrLen() : 0; DPRINTF(EthernetDesc, "lpe: %d Packet Length: %d offset: %d srrctl: %#x " "hdr addr: %#x Hdr Size: %d desc addr: %#x Desc Size: %d\n", @@ -1302,7 +1302,7 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet, int pkt_offset) int max_to_copy = std::min(packet->length - split_point, buf_len); bytesCopied += max_to_copy + split_point; - + DPRINTF(EthernetDesc, "Hdr split: splitting at %d\n", split_point); igbe->dmaWrite(pciToDma(desc->adv_read.hdr), @@ -1431,7 +1431,7 @@ IGbE::RxDescCache::pktComplete() desc->adv_wb.status = htole(status); desc->adv_wb.errors = htole(ext_err); // no vlan support - desc->adv_wb.vlan_tag = htole(0); + desc->adv_wb.vlan_tag = htole(0); break; default: panic("Unimplemnted RX receive buffer type %d\n", @@ -1514,7 +1514,7 @@ IGbE::RxDescCache::hasOutstandingEvents() return pktEvent.scheduled() || wbEvent.scheduled() || fetchEvent.scheduled() || pktHdrEvent.scheduled() || pktDataEvent.scheduled(); - + } void @@ -1561,7 +1561,7 @@ IGbE::TxDescCache::processContextDesc() { assert(unusedCache.size()); TxDesc *desc; - + DPRINTF(EthernetDesc, "Checking and processing context descriptors\n"); while (!useTso && unusedCache.size() && @@ -1569,14 +1569,14 @@ IGbE::TxDescCache::processContextDesc() DPRINTF(EthernetDesc, "Got context descriptor type...\n"); desc = unusedCache.front(); - DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", + DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", desc->d1, desc->d2); - + // is this going to be a tcp or udp packet? isTcp = TxdOp::tcp(desc) ? true : false; - // setup all the TSO variables, they'll be ignored if we don't use + // setup all the TSO variables, they'll be ignored if we don't use // tso for this connection tsoHeaderLen = TxdOp::hdrlen(desc); tsoMss = TxdOp::mss(desc); @@ -1607,10 +1607,10 @@ IGbE::TxDescCache::processContextDesc() return; desc = unusedCache.front(); - if (!useTso && TxdOp::isType(desc, TxdOp::TXD_ADVDATA) && + if (!useTso && TxdOp::isType(desc, TxdOp::TXD_ADVDATA) && TxdOp::tse(desc)) { DPRINTF(EthernetDesc, "TCP offload(adv) enabled for packet " - "hdrlen: %d mss: %d paylen %d\n", + "hdrlen: %d mss: %d paylen %d\n", tsoHeaderLen, tsoMss, TxdOp::getTsoLen(desc)); useTso = true; tsoTotalLen = TxdOp::getTsoLen(desc); @@ -1663,7 +1663,7 @@ IGbE::TxDescCache::getPacketSize(EthPacketPtr p) { if (!unusedCache.size()) return 0; - + DPRINTF(EthernetDesc, "Starting processing of descriptor\n"); assert(!useTso || tsoLoadedHeader); @@ -1676,14 +1676,14 @@ IGbE::TxDescCache::getPacketSize(EthPacketPtr p) "used: %d loaded hdr: %d\n", useTso, tsoHeaderLen, tsoMss, tsoTotalLen, tsoUsedLen, tsoLoadedHeader); - if (tsoPktHasHeader) + if (tsoPktHasHeader) tsoCopyBytes = std::min((tsoMss + tsoHeaderLen) - p->length, TxdOp::getLen(desc) - tsoDescBytesUsed); else tsoCopyBytes = std::min(tsoMss, - TxdOp::getLen(desc) - tsoDescBytesUsed); + TxdOp::getLen(desc) - tsoDescBytesUsed); unsigned pkt_size = - tsoCopyBytes + (tsoPktHasHeader ? 0 : tsoHeaderLen); + tsoCopyBytes + (tsoPktHasHeader ? 0 : tsoHeaderLen); DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d " "this descLen: %d\n", @@ -1716,7 +1716,7 @@ IGbE::TxDescCache::getPacketData(EthPacketPtr p) pktWaiting = true; DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d\n", p->length); - + if (useTso) { assert(tsoLoadedHeader); if (!tsoPktHasHeader) { @@ -1728,7 +1728,7 @@ IGbE::TxDescCache::getPacketData(EthPacketPtr p) tsoPktHasHeader = true; } } - + if (useTso) { DPRINTF(EthernetDesc, "Starting DMA of packet at offset %d length: %d\n", @@ -1777,10 +1777,10 @@ IGbE::TxDescCache::pktComplete() tsoDescBytesUsed, tsoCopyBytes); } else pktPtr->length += TxdOp::getLen(desc); - - if ((!TxdOp::eop(desc) && !useTso) || + + if ((!TxdOp::eop(desc) && !useTso) || (pktPtr->length < ( tsoMss + tsoHeaderLen) && tsoTotalLen != tsoUsedLen && useTso)) { assert(!useTso || (tsoDescBytesUsed == TxdOp::getLen(desc))); @@ -1825,8 +1825,8 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "TSO: Modifying IP header. Id + %d\n", tsoPkts); ip->id(ip->id() + tsoPkts++); - ip->len(pktPtr->length - EthPtr(pktPtr)->size()); - + ip->len(pktPtr->length - EthPtr(pktPtr)->size()); + TcpPtr tcp(ip); if (tcp) { DPRINTF(EthernetDesc, @@ -1945,12 +1945,12 @@ IGbE::TxDescCache::pktComplete() } void -IGbE::TxDescCache::actionAfterWb() +IGbE::TxDescCache::actionAfterWb() { DPRINTF(EthernetDesc, "actionAfterWb() completionEnabled: %d\n", completionEnabled); igbe->postInterrupt(iGbReg::IT_TXDW); - if (completionEnabled) { + if (completionEnabled) { descEnd = igbe->regs.tdh(); DPRINTF(EthernetDesc, "Completion writing back value: %d to addr: %#x\n", descEnd, diff --git a/src/dev/net/i8254xGBe.hh b/src/dev/net/i8254xGBe.hh index e35744459..ed0bf4713 100644 --- a/src/dev/net/i8254xGBe.hh +++ b/src/dev/net/i8254xGBe.hh @@ -414,7 +414,7 @@ class IGbE : public EtherDevice if (!igbe->txTick && igbe->drainState() == DrainState::Running) fetchDescriptors(); } - + bool pktDone; @@ -424,7 +424,7 @@ class IGbE : public EtherDevice Addr completionAddress; bool completionEnabled; uint32_t descEnd; - + // tso variables bool useTso; @@ -491,7 +491,7 @@ class IGbE : public EtherDevice void completionWriteback(Addr a, bool enabled) { DPRINTF(EthernetDesc, - "Completion writeback Addr: %#x enabled: %d\n", + "Completion writeback Addr: %#x enabled: %d\n", a, enabled); completionAddress = a; completionEnabled = enabled; diff --git a/src/dev/net/i8254xGBe_defs.hh b/src/dev/net/i8254xGBe_defs.hh index 79a9413da..0bb29e56b 100644 --- a/src/dev/net/i8254xGBe_defs.hh +++ b/src/dev/net/i8254xGBe_defs.hh @@ -187,7 +187,7 @@ enum IntTypes // Receive Descriptor struct struct RxDesc { - union { + union { struct { Addr buf; uint16_t len; @@ -250,7 +250,7 @@ inline bool rs(TxDesc *d) { return bits(d->d2, 27,27); } inline bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); } inline bool tse(TxDesc *d) { if (isTypes(d, TXD_CNXT, TXD_DATA)) - return bits(d->d2, 26,26); + return bits(d->d2, 26,26); if (isType(d, TXD_ADVDATA)) return bits(d->d2, 31, 31); return false; @@ -275,10 +275,10 @@ inline int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); } inline int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); } inline int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); } inline int hdrlen(TxDesc *d) { - assert(isContext(d)); + assert(isContext(d)); if (!isAdvDesc(d)) return bits(d->d2,47,40); - return bits(d->d2, 47,40) + bits(d->d1, 8,0) + bits(d->d1, 15, 9); + return bits(d->d2, 47,40) + bits(d->d1, 8,0) + bits(d->d1, 15, 9); } inline int getTsoLen(TxDesc *d) { assert(isType(d, TXD_ADVDATA)); return bits(d->d2, 63,46); } @@ -744,9 +744,9 @@ struct Regs : public Serializable { struct FWSM : public Reg<uint32_t> { // 0x5B54 FWSM register using Reg<uint32_t>::operator=; - ADD_FIELD32(eep_fw_semaphore,0,1); - ADD_FIELD32(fw_mode, 1,3); - ADD_FIELD32(ide, 4,1); + ADD_FIELD32(eep_fw_semaphore,0,1); + ADD_FIELD32(fw_mode, 1,3); + ADD_FIELD32(ide, 4,1); ADD_FIELD32(sol, 5,1); ADD_FIELD32(eep_roload, 6,1); ADD_FIELD32(reserved, 7,8); diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc index ddd61c395..8aef93223 100644 --- a/src/dev/x86/i8042.cc +++ b/src/dev/x86/i8042.cc @@ -490,7 +490,7 @@ X86ISA::I8042::serialize(CheckpointOut &cp) const { uint8_t statusRegData = statusReg.__data; uint8_t commandByteData = commandByte.__data; - + SERIALIZE_SCALAR(dataPort); SERIALIZE_SCALAR(commandPort); SERIALIZE_SCALAR(statusRegData); diff --git a/src/dev/x86/i8254.hh b/src/dev/x86/i8254.hh index 8243f8391..e1de8a1bb 100644 --- a/src/dev/x86/i8254.hh +++ b/src/dev/x86/i8254.hh @@ -61,11 +61,11 @@ class I8254 : public BasicPioDevice {} }; - + X86Intel8254Timer pit; IntSourcePin *intPin; - + void counterInterrupt(unsigned int num); public: diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh index 65ad8727d..1a49bb3e2 100644 --- a/src/dev/x86/intdev.hh +++ b/src/dev/x86/intdev.hh @@ -210,7 +210,7 @@ class IntSourcePin : public SimObject pin.device->raiseInterruptPin(pin.number); } } - + void lower() { diff --git a/src/mem/mport.hh b/src/mem/mport.hh index 9bc437c52..72d0b0962 100644 --- a/src/mem/mport.hh +++ b/src/mem/mport.hh @@ -49,7 +49,7 @@ /* * This file defines a port class which is used for sending and receiving * messages. These messages are atomic units which don't interact and - * should be smaller than a cache block. This class is based on + * should be smaller than a cache block. This class is based on * the underpinnings of SimpleTimingPort, but it tweaks some of the external * functions. */ diff --git a/src/mem/ruby/network/Topology.cc b/src/mem/ruby/network/Topology.cc index 8118770ea..757efe063 100644 --- a/src/mem/ruby/network/Topology.cc +++ b/src/mem/ruby/network/Topology.cc @@ -57,7 +57,7 @@ Topology::Topology(uint32_t num_routers, // analyze both the internal and external links, create data structures // Note that the python created links are bi-directional, but that the - // topology and networks utilize uni-directional links. Thus each + // topology and networks utilize uni-directional links. Thus each // BasicLink is converted to two calls to add link, on for each direction for (vector<BasicExtLink*>::const_iterator i = ext_links.begin(); i != ext_links.end(); ++i) { @@ -106,7 +106,7 @@ Topology::createLinks(Network *net) i != m_link_map.end(); ++i) { std::pair<SwitchID, SwitchID> src_dest = (*i).first; max_switch_id = max(max_switch_id, src_dest.first); - max_switch_id = max(max_switch_id, src_dest.second); + max_switch_id = max(max_switch_id, src_dest.second); } // Initialize weight, latency, and inter switched vectors @@ -133,7 +133,7 @@ Topology::createLinks(Network *net) component_latencies[src][dst] = link->m_latency; topology_weights[src][dst] = link->m_weight; } - + // Walk topology and hookup the links Matrix dist = shortest_path(topology_weights, component_latencies, component_inter_switches); @@ -151,12 +151,12 @@ Topology::createLinks(Network *net) } void -Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, +Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, LinkDirection dir) { assert(src <= m_number_of_switches+m_nodes+m_nodes); assert(dest <= m_number_of_switches+m_nodes+m_nodes); - + std::pair<int, int> src_dest_pair; LinkEntry link_entry; @@ -176,7 +176,7 @@ Topology::makeLink(Network *net, SwitchID src, SwitchID dest, assert(src >= 2 * m_nodes || dest >= 2 * m_nodes); std::pair<int, int> src_dest; - LinkEntry link_entry; + LinkEntry link_entry; if (src < m_nodes) { src_dest.first = src; diff --git a/src/mem/ruby/network/Topology.hh b/src/mem/ruby/network/Topology.hh index 7fa0914a1..d55ba99a9 100644 --- a/src/mem/ruby/network/Topology.hh +++ b/src/mem/ruby/network/Topology.hh @@ -53,7 +53,7 @@ class Network; typedef std::vector<std::vector<int> > Matrix; -struct LinkEntry +struct LinkEntry { BasicLink *link; LinkDirection direction; diff --git a/src/mem/ruby/network/fault_model/FaultModel.cc b/src/mem/ruby/network/fault_model/FaultModel.cc index 83679984d..7be5bcd49 100644 --- a/src/mem/ruby/network/fault_model/FaultModel.cc +++ b/src/mem/ruby/network/fault_model/FaultModel.cc @@ -31,7 +31,7 @@ /* * Official Tool Website: www.mit.edu/~kaisopos/FaultModel * - * If you use our tool for academic research, we request that you cite: + * If you use our tool for academic research, we request that you cite: * Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling * System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. * Proceedings of the 48th Design Automation Conference (DAC'11) @@ -45,7 +45,7 @@ // GEM5 includes #include "FaultModel.hh" -#include "base/misc.hh" +#include "base/misc.hh" using namespace std; @@ -55,18 +55,18 @@ using namespace std; FaultModel::FaultModel(const Params *p) : SimObject(p) { // read configurations into "configurations" vector - // format: <buff/vc> <vcs> <10 fault types> + // format: <buff/vc> <vcs> <10 fault types> bool more_records = true; for (int i = 0; more_records; i += (fields_per_conf_record)){ system_conf configuration; - configuration.buff_per_vc = + configuration.buff_per_vc = p->baseline_fault_vector_database[i + conf_record_buff_per_vc]; - configuration.vcs = + configuration.vcs = p->baseline_fault_vector_database[i + conf_record_vcs]; - for (int fault_index = 0; fault_index < number_of_fault_types; + for (int fault_index = 0; fault_index < number_of_fault_types; fault_index++){ - configuration.fault_type[fault_index] = - p->baseline_fault_vector_database[i + + configuration.fault_type[fault_index] = + p->baseline_fault_vector_database[i + conf_record_first_fault_type + fault_index] / 100; } configurations.push_back(configuration); @@ -79,13 +79,13 @@ FaultModel::FaultModel(const Params *p) : SimObject(p) // format: <temperature> <weight> more_records = true; for (int i = 0; more_records; i += (fields_per_temperature_record)){ - int record_temperature = + int record_temperature = p->temperature_weights_database[i + temperature_record_temp]; int record_weight = p->temperature_weights_database[i + temperature_record_weight]; static int first_record = true; if (first_record){ - for (int temperature = 0; temperature < record_temperature; + for (int temperature = 0; temperature < record_temperature; temperature++){ temperature_weights.push_back(0); } @@ -93,7 +93,7 @@ FaultModel::FaultModel(const Params *p) : SimObject(p) } assert(record_temperature == temperature_weights.size()); temperature_weights.push_back(record_weight); - if (p->temperature_weights_database[i + + if (p->temperature_weights_database[i + fields_per_temperature_record] < 0){ more_records = false; } @@ -131,16 +131,16 @@ FaultModel::fault_type_to_string(int ft) } -int -FaultModel::declare_router(int number_of_inputs, - int number_of_outputs, - int number_of_vcs_per_input, - int number_of_buff_per_data_vc, +int +FaultModel::declare_router(int number_of_inputs, + int number_of_outputs, + int number_of_vcs_per_input, + int number_of_buff_per_data_vc, int number_of_buff_per_ctrl_vc) { // check inputs (are they legal?) if (number_of_inputs <= 0 || number_of_outputs <= 0 || - number_of_vcs_per_input <= 0 || number_of_buff_per_data_vc <= 0 || + number_of_vcs_per_input <= 0 || number_of_buff_per_data_vc <= 0 || number_of_buff_per_ctrl_vc <= 0){ fatal("Fault Model: ERROR in argument of FaultModel_declare_router!"); } @@ -156,7 +156,7 @@ FaultModel::declare_router(int number_of_inputs, // link the router to a DB record int record_hit = -1; - for (int record = 0; record < configurations.size(); record++){ + for (int record = 0; record < configurations.size(); record++){ if ((configurations[record].buff_per_vc == number_of_buffers_per_vc)&& (configurations[record].vcs == total_vcs)){ record_hit = record; @@ -172,8 +172,8 @@ FaultModel::declare_router(int number_of_inputs, return router_index++; } -bool -FaultModel::fault_vector(int routerID, +bool +FaultModel::fault_vector(int routerID, int temperature_input, float fault_vector[]) { @@ -182,7 +182,7 @@ FaultModel::fault_vector(int routerID, // is the routerID recorded? if (routerID < 0 || routerID >= ((int) routers.size())){ warn("Fault Model: ERROR! unknown router ID argument."); - fatal("Fault Model: Did you enable the fault model flag)?"); + fatal("Fault Model: Did you enable the fault model flag)?"); } // is the temperature too high/too low? @@ -201,14 +201,14 @@ FaultModel::fault_vector(int routerID, // recover the router record and return its fault vector for (int i = 0; i < number_of_fault_types; i++){ - fault_vector[i] = routers[routerID].fault_type[i] * + fault_vector[i] = routers[routerID].fault_type[i] * ((float)temperature_weights[temperature]); } return ok; } -bool -FaultModel::fault_prob(int routerID, +bool +FaultModel::fault_prob(int routerID, int temperature_input, float *aggregate_fault_prob) { @@ -218,7 +218,7 @@ FaultModel::fault_prob(int routerID, // is the routerID recorded? if (routerID < 0 || routerID >= ((int) routers.size())){ warn("Fault Model: ERROR! unknown router ID argument."); - fatal("Fault Model: Did you enable the fault model flag)?"); + fatal("Fault Model: Did you enable the fault model flag)?"); } // is the temperature too high/too low? @@ -237,8 +237,8 @@ FaultModel::fault_prob(int routerID, // recover the router record and return its aggregate fault probability for (int i = 0; i < number_of_fault_types; i++){ - *aggregate_fault_prob= *aggregate_fault_prob * - ( 1.0 - (routers[routerID].fault_type[i] * + *aggregate_fault_prob= *aggregate_fault_prob * + ( 1.0 - (routers[routerID].fault_type[i] * ((float)temperature_weights[temperature])) ); } *aggregate_fault_prob = 1.0 - *aggregate_fault_prob; @@ -246,7 +246,7 @@ FaultModel::fault_prob(int routerID, } // this function is used only for debugging purposes -void +void FaultModel::print(void) { cout << "--- PRINTING configurations ---\n"; @@ -254,10 +254,10 @@ FaultModel::print(void) cout << "(" << record << ") "; cout << "VCs=" << configurations[record].vcs << " "; cout << "Buff/VC=" << configurations[record].buff_per_vc << " ["; - for (int fault_type_num = 0; - fault_type_num < number_of_fault_types; + for (int fault_type_num = 0; + fault_type_num < number_of_fault_types; fault_type_num++){ - cout << (100 * configurations[record].fault_type[fault_type_num]); + cout << (100 * configurations[record].fault_type[fault_type_num]); cout << "% "; } cout << "]\n"; diff --git a/src/mem/ruby/network/fault_model/FaultModel.hh b/src/mem/ruby/network/fault_model/FaultModel.hh index c099220ca..f2f355b3c 100644 --- a/src/mem/ruby/network/fault_model/FaultModel.hh +++ b/src/mem/ruby/network/fault_model/FaultModel.hh @@ -31,7 +31,7 @@ /* * Official Tool Website: www.mit.edu/~kaisopos/FaultModel * - * If you use our tool for academic research, we request that you cite: + * If you use our tool for academic research, we request that you cite: * Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling * System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. * Proceedings of the 48th Design Automation Conference (DAC'11) @@ -63,7 +63,7 @@ class FaultModel : public SimObject /********** THE FAULT TYPES SUPPORTED BY THE FAULT MODEL ***************/ /************************************************************************/ - enum fault_type + enum fault_type { data_corruption__few_bits, data_corruption__all_bits, @@ -105,27 +105,27 @@ class FaultModel : public SimObject float fault_type[number_of_fault_types]; }; - int declare_router(int number_of_inputs, - int number_of_outputs, - int number_of_vcs_per_vnet, - int number_of_buff_per_data_vc, + int declare_router(int number_of_inputs, + int number_of_outputs, + int number_of_vcs_per_vnet, + int number_of_buff_per_data_vc, int number_of_buff_per_ctrl_vc); std::string fault_type_to_string(int fault_type_index); - - // the following 2 functions are called at runtime, to get the probability - // of each fault type (fault_vector) or the aggregate fault probability + + // the following 2 functions are called at runtime, to get the probability + // of each fault type (fault_vector) or the aggregate fault probability // (fault_prob). Note: the probability values are provided by reference // (in the variables fault_vector[] & aggregate_fault_prob respectively). - // Both functions also return a success flag (which is always true if + // Both functions also return a success flag (which is always true if // temperature ranges from 0C to 125C) - bool fault_vector(int routerID, - int temperature, + bool fault_vector(int routerID, + int temperature, float fault_vector[]); bool fault_prob(int routerID, - int temperature, + int temperature, float *aggregate_fault_prob); // for debugging purposes diff --git a/src/mem/ruby/network/fault_model/FaultModel.py b/src/mem/ruby/network/fault_model/FaultModel.py index b1532150b..ef6447ef9 100644 --- a/src/mem/ruby/network/fault_model/FaultModel.py +++ b/src/mem/ruby/network/fault_model/FaultModel.py @@ -28,7 +28,7 @@ # Official Tool Website: www.mit.edu/~kaisopos/FaultModel # -# If you use our tool for academic research, we request that you cite: +# If you use our tool for academic research, we request that you cite: # Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling # System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. # Proceedings of the 48th Design Automation Conference (DAC'11) @@ -38,9 +38,9 @@ from m5.SimObject import SimObject class FaultModel(SimObject): type = 'FaultModel' - cxx_class = 'FaultModel' + cxx_class = 'FaultModel' cxx_header = "mem/ruby/network/fault_model/FaultModel.hh" - + baseline_fault_vector_database = VectorParam.Float([ 5, 40, 0.080892, 0.109175, 0.018864, 0.130408, 0.059724, 0.077571, 0.034830, 0.083430, 0.067500, 0.121500, 5, 39, 0.062640, 0.089100, 0.016821, 0.109620, 0.051462, 0.060210, 0.029700, 0.076140, 0.062100, 0.116100, diff --git a/src/mem/ruby/network/fault_model/SConscript b/src/mem/ruby/network/fault_model/SConscript index ade3eca64..0f390bd6f 100644 --- a/src/mem/ruby/network/fault_model/SConscript +++ b/src/mem/ruby/network/fault_model/SConscript @@ -28,7 +28,7 @@ # Official Tool Website: www.mit.edu/~kaisopos/FaultModel # -# If you use our tool for academic research, we request that you cite: +# If you use our tool for academic research, we request that you cite: # Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling # System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. # Proceedings of the 48th Design Automation Conference (DAC'11) diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py index 4a957b66e..c7833ee96 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py @@ -55,7 +55,7 @@ class GarnetIntLink_d(BasicIntLink): # forward links and two backward flow-control links, one per direction nls = [] # In uni-directional link - nls.append(NetworkLink_d()); + nls.append(NetworkLink_d()); # Out uni-directional link nls.append(NetworkLink_d()); network_links = VectorParam.NetworkLink_d(nls, "forward links") diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh index 9b384596e..99a0046ce 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh @@ -71,9 +71,9 @@ class Router_d : public BasicRouter int get_num_outports() { return m_output_unit.size(); } int get_id() { return m_id; } - void init_net_ptr(GarnetNetwork_d* net_ptr) - { - m_network_ptr = net_ptr; + void init_net_ptr(GarnetNetwork_d* net_ptr) + { + m_network_ptr = net_ptr; } GarnetNetwork_d* get_net_ptr() { return m_network_ptr; } @@ -95,13 +95,13 @@ class Router_d : public BasicRouter void collateStats(); void resetStats(); - bool get_fault_vector(int temperature, float fault_vector[]){ - return m_network_ptr->fault_model->fault_vector(m_id, temperature, - fault_vector); + bool get_fault_vector(int temperature, float fault_vector[]){ + return m_network_ptr->fault_model->fault_vector(m_id, temperature, + fault_vector); } - bool get_aggregate_fault_probability(int temperature, + bool get_aggregate_fault_probability(int temperature, float *aggregate_fault_prob){ - return m_network_ptr->fault_model->fault_prob(m_id, temperature, + return m_network_ptr->fault_model->fault_prob(m_id, temperature, aggregate_fault_prob); } diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py index 9903c9cd6..1fefca2c5 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py @@ -53,7 +53,7 @@ class GarnetIntLink(BasicIntLink): # forward links and no backward flow-control links nls = [] # In uni-directional link - nls.append(NetworkLink()); + nls.append(NetworkLink()); # Out uni-directional link nls.append(NetworkLink()); network_links = VectorParam.NetworkLink(nls, "forward links") diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh index 46f62c04f..e9b94809f 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh @@ -60,14 +60,14 @@ class GarnetNetwork : public BaseGarnetNetwork void print(std::ostream& out) const; // Methods used by Topology to setup the network - void makeOutLink(SwitchID src, NodeID dest, BasicLink* link, - LinkDirection direction, + void makeOutLink(SwitchID src, NodeID dest, BasicLink* link, + LinkDirection direction, const NetDest& routing_table_entry); - void makeInLink(NodeID src, SwitchID dest, BasicLink* link, - LinkDirection direction, + void makeInLink(NodeID src, SwitchID dest, BasicLink* link, + LinkDirection direction, const NetDest& routing_table_entry); void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection direction, + LinkDirection direction, const NetDest& routing_table_entry); //! Function for performing a functional read. The return value diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh b/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh index 11a860b11..c225e8b71 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh @@ -68,9 +68,9 @@ class Router : public BasicRouter, public FlexibleConsumer void print(std::ostream& out) const; - void init_net_ptr(GarnetNetwork* net_ptr) - { - m_net_ptr = net_ptr; + void init_net_ptr(GarnetNetwork* net_ptr) + { + m_net_ptr = net_ptr; } bool functionalRead(Packet *); diff --git a/src/mem/ruby/network/simple/SimpleLink.cc b/src/mem/ruby/network/simple/SimpleLink.cc index 57ae6c79e..04a60d888 100644 --- a/src/mem/ruby/network/simple/SimpleLink.cc +++ b/src/mem/ruby/network/simple/SimpleLink.cc @@ -32,9 +32,9 @@ SimpleExtLink::SimpleExtLink(const Params *p) : BasicExtLink(p) { // For the simple links, the bandwidth factor translates to the - // bandwidth multiplier. The multipiler, in combination with the - // endpoint bandwidth multiplier - message size multiplier ratio, - // determines the link bandwidth in bytes + // bandwidth multiplier. The multipiler, in combination with the + // endpoint bandwidth multiplier - message size multiplier ratio, + // determines the link bandwidth in bytes m_bw_multiplier = p->bandwidth_factor; } @@ -54,9 +54,9 @@ SimpleIntLink::SimpleIntLink(const Params *p) : BasicIntLink(p) { // For the simple links, the bandwidth factor translates to the - // bandwidth multiplier. The multipiler, in combination with the - // endpoint bandwidth multiplier - message size multiplier ratio, - // determines the link bandwidth in bytes + // bandwidth multiplier. The multipiler, in combination with the + // endpoint bandwidth multiplier - message size multiplier ratio, + // determines the link bandwidth in bytes m_bw_multiplier = p->bandwidth_factor; } diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py b/src/mem/slicc/ast/StallAndWaitStatementAST.py index 6ab2888b7..ad261e26f 100644 --- a/src/mem/slicc/ast/StallAndWaitStatementAST.py +++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py @@ -33,7 +33,7 @@ class StallAndWaitStatementAST(StatementAST): super(StatementAST, self).__init__(slicc) self.in_port = in_port self.address = address - + def __repr__(self): return "[StallAndWaitStatementAst: %r]" % self.in_port diff --git a/src/mem/slicc/ast/TypeFieldEnumAST.py b/src/mem/slicc/ast/TypeFieldEnumAST.py index 5ebb516d3..b9a8ae80f 100644 --- a/src/mem/slicc/ast/TypeFieldEnumAST.py +++ b/src/mem/slicc/ast/TypeFieldEnumAST.py @@ -41,7 +41,7 @@ class TypeFieldEnumAST(TypeFieldAST): def generate(self, type): if str(type) == "State": self.error("States must in a State Declaration, not a normal enum.") - + # Add enumeration if not type.addEnum(self.field_id, self.pairs_ast.pairs): self.error("Duplicate enumeration: %s:%s" % (type, self.field_id)) diff --git a/src/mem/slicc/ast/TypeFieldStateAST.py b/src/mem/slicc/ast/TypeFieldStateAST.py index d2b253218..deac143bb 100644 --- a/src/mem/slicc/ast/TypeFieldStateAST.py +++ b/src/mem/slicc/ast/TypeFieldStateAST.py @@ -43,7 +43,7 @@ class TypeFieldStateAST(TypeFieldAST): def generate(self, type): if not str(type) == "State": self.error("State Declaration must be of type State.") - + # Add enumeration if not type.addEnum(self.field_id, self.pairs_ast.pairs): self.error("Duplicate enumeration: %s:%s" % (type, self.field_id)) diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py index 66ebb3cfe..3ff69d851 100644 --- a/src/python/m5/util/__init__.py +++ b/src/python/m5/util/__init__.py @@ -174,7 +174,7 @@ def readCommand(cmd, **kwargs): no_exception = 'exception' in kwargs exception = kwargs.pop('exception', None) - + kwargs.setdefault('shell', False) kwargs.setdefault('stdout', PIPE) kwargs.setdefault('stderr', STDOUT) diff --git a/src/python/swig/event.i b/src/python/swig/event.i index cc72794ed..60a789c1a 100644 --- a/src/python/swig/event.i +++ b/src/python/swig/event.i @@ -57,11 +57,11 @@ pyevent->incref(); $self->schedule(event, when); } - + void deschedule(Event *event) { - $self->deschedule(event); + $self->deschedule(event); // Now that we're removing the python object from the event // queue, we need to decrement its reference count. diff --git a/src/sim/Root.py b/src/sim/Root.py index c6f7cfba6..776222b9c 100644 --- a/src/sim/Root.py +++ b/src/sim/Root.py @@ -50,7 +50,7 @@ class Root(SimObject): # args. Seems like a bad design but that's the way it is. Root._the_instance = SimObject.__new__(cls) return Root._the_instance - + @classmethod def getInstance(cls): return Root._the_instance diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc index 698ecd116..7c2648c64 100644 --- a/src/sim/eventq.cc +++ b/src/sim/eventq.cc @@ -263,9 +263,9 @@ Event::unserialize(CheckpointIn &cp) // Old checkpoints had no concept of the Initialized flag // so restoring from old checkpoints always fail. - // Events are initialized on construction but original code - // "flags = _flags" would just overwrite the initialization. - // So, read in the checkpoint flags, but then set the Initialized + // Events are initialized on construction but original code + // "flags = _flags" would just overwrite the initialization. + // So, read in the checkpoint flags, but then set the Initialized // flag on top of it in order to avoid failures. assert(initialized()); flags = _flags; diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index 184d6ec3b..eeb392153 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -95,7 +95,7 @@ inline void curEventQueue(EventQueue *q) { _curEventQueue = q; } */ class EventBase { - protected: + protected: typedef unsigned short FlagsType; typedef ::Flags<FlagsType> Flags; diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh index 6819c2199..7b15d1f91 100644 --- a/src/sim/insttracer.hh +++ b/src/sim/insttracer.hh @@ -183,7 +183,7 @@ class InstRecord void setPredicate(bool val) { predicate = val; } virtual void dump() = 0; - + public: Tick getWhen() const { return when; } ThreadContext *getThread() const { return thread; } diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 67c47ce77..12df08f2d 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -645,7 +645,7 @@ switchcpu(ThreadContext *tc) } // -// This function is executed when annotated work items begin. Depending on +// This function is executed when annotated work items begin. Depending on // what the user specified at the command line, the simulation may exit and/or // take a checkpoint when a certain work item begins. // @@ -708,7 +708,7 @@ workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid) } // -// This function is executed when annotated work items end. Depending on +// This function is executed when annotated work items end. Depending on // what the user specified at the command line, the simulation may exit and/or // take a checkpoint when a certain work item ends. // diff --git a/src/unittest/cprintftest.cc b/src/unittest/cprintftest.cc index ee5701d13..7e6d2f2d4 100644 --- a/src/unittest/cprintftest.cc +++ b/src/unittest/cprintftest.cc @@ -48,7 +48,7 @@ main() int length = 11; char bar[length + 1]; bar[length] = 0; - + memcpy(bar, _bar.c_str(), length); warn("%s\n", bar); diff --git a/system/alpha/console/console.c b/system/alpha/console/console.c index f57ce054f..847c375b0 100644 --- a/system/alpha/console/console.c +++ b/system/alpha/console/console.c @@ -419,7 +419,7 @@ unixBoot(int argc, char **argv) rpb = (struct rpb *)unix_boot_alloc(HWRPB_PAGES); - mdt_bitmap = (unsigned char *)unix_boot_alloc(mdt_bitmap_pages); + mdt_bitmap = (unsigned char *)unix_boot_alloc(mdt_bitmap_pages); first = (ulong *)unix_boot_alloc(1); second = (ulong *)unix_boot_alloc(1); third_rpb = (ulong *)unix_boot_alloc(1); diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index cbe41301c..221d28b2e 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -76,7 +76,7 @@ cpus = [ MemTest(percent_functional=50, # overwrite options.num_cpus with the nb_cores value options.num_cpus = nb_cores - + # system simulated system = System(cpu = cpus) # Dummy voltage domain for all our clock domains diff --git a/util/checkpoint-tester.py b/util/checkpoint-tester.py index d5d8004a2..530462758 100755 --- a/util/checkpoint-tester.py +++ b/util/checkpoint-tester.py @@ -109,7 +109,7 @@ for dir in dirs: cpts.append(int(match.group(1))) cpts.sort() - + # We test by loading checkpoint N, simulating to (and dumping at) # checkpoint N+1, then comparing the resulting checkpoint with the # original checkpoint N+1. Thus the number of tests we can run is one @@ -132,4 +132,4 @@ for i in range(1, len(cpts)): print diffout.read(), diffout.close() - + diff --git a/util/compile b/util/compile index 7f9b5d447..627e78b74 100755 --- a/util/compile +++ b/util/compile @@ -147,7 +147,7 @@ add_option('-E', "--experimental", action='store_true', default=False, help="enable experimental builds") add_option('-v', "--verbose", default=False, action='store_true', help="be verbose") - + set_group("Output binary types") bool_option("debug", default=False, help="compile debug binaries") bool_option("opt", default=False, help="compile opt binaries") diff --git a/util/m5/m5.c b/util/m5/m5.c index 522268410..f773153da 100644 --- a/util/m5/m5.c +++ b/util/m5/m5.c @@ -285,7 +285,7 @@ do_pin(int argc, char *argv[]) if (argc < 2) usage(); - cpu_set_t mask; + cpu_set_t mask; CPU_ZERO(&mask); const char *sep = ","; @@ -293,7 +293,7 @@ do_pin(int argc, char *argv[]) while (target) { CPU_SET(atoi(target), &mask); target = strtok(NULL, sep); - } + } if (sched_setaffinity(0, sizeof(cpu_set_t), &mask) < 0) err(1, "setaffinity"); @@ -30,7 +30,7 @@ # Ali Saidi # Important! -# This script expects a simple $ prompt, if you are using a shell other than +# This script expects a simple $ prompt, if you are using a shell other than # sh which defaults to this you'll need to add something like the following # to your bashrc/bash_profile script: #if [ "$OAR_USER" = "xxxx" ]; then @@ -97,11 +97,11 @@ class Shell(pexpect.spawn): def __init__(self, cmd): # initialize base pexpect.spawn object - try: + try: pexpect.spawn.__init__(self, cmd) - except pexpect.ExceptionPexpect, exc: - print "%s:" % progname, exc - sys.exit(1) + except pexpect.ExceptionPexpect, exc: + print "%s:" % progname, exc + sys.exit(1) # full_output accumulates the full output of the session self.full_output = "" self.quick_timeout = 15 @@ -146,17 +146,17 @@ class Shell(pexpect.spawn): (output, status) = shell.do_command('[ -d %s ]' % dirname, self.quick_timeout) return status == 0 - + # Don't actually try to close it.. just wait until it closes by itself - # We can't actually kill the pid which is what it's trying to do, and if - # we call wait we could be in an unfortunate situation of it printing input + # We can't actually kill the pid which is what it's trying to do, and if + # we call wait we could be in an unfortunate situation of it printing input # right as we call wait, so the input is never read and the process never ends def safe_close(self): count = 0 while self.isalive() and count < 10: time.sleep(1) self.close(force=False) - + # Spawn the interactive pool job. # Hack to do link on poolfs... disabled for now since diff --git a/util/statetrace/SConstruct b/util/statetrace/SConstruct index 5909772c6..ce914d79d 100644 --- a/util/statetrace/SConstruct +++ b/util/statetrace/SConstruct @@ -35,7 +35,7 @@ scons build/arm/statetrace You may need a cross compiler in order to build statetrace successfully. To specify an alternative compiler, set the CXX scons argument on the command -line. The CXX environment variable is NOT considered when selecting the +line. The CXX environment variable is NOT considered when selecting the compiler. To override the compiler for a particular target ISA, set the <arch>CXX scons argument. For example, to build both the AMD64 version and the ARM version at the same time using the system compiler for the AMD64 |