diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-28 16:53:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-28 16:53:48 -0400 |
| commit | ff2d58f935c434e89a499474d3bda76f476e6d25 (patch) | |
| tree | 3d895dc40952ec47b3388dded8072bf988b3c49c | |
| parent | ec41000dadd5256fd90f0bfdc97264946e50a3aa (diff) | |
| download | gem5-ff2d58f935c434e89a499474d3bda76f476e6d25.tar.xz | |
stats: Update stats to reflect ARM fixes
As a result of the fixes, the full-system dual-core ARM regressions
are slightly changed. Hopefully this also means there will no longer
be any discrepancies between the results observed on different hosts.
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 3651 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 4909 |
2 files changed, 4266 insertions, 4294 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 59143a518..e666b7d0c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,168 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.658500 # Number of seconds simulated -sim_ticks 2658500429500 # Number of ticks simulated -final_tick 2658500429500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.658488 # Number of seconds simulated +sim_ticks 2658488068000 # Number of ticks simulated +final_tick 2658488068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100914 # Simulator instruction rate (inst/s) -host_op_rate 121517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4256503307 # Simulator tick rate (ticks/s) -host_mem_usage 437672 # Number of bytes of host memory used -host_seconds 624.57 # Real time elapsed on the host -sim_insts 63028509 # Number of instructions simulated -sim_ops 75896503 # Number of ops (including micro ops) simulated +host_inst_rate 84054 # Simulator instruction rate (inst/s) +host_op_rate 101215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3545231727 # Simulator tick rate (ticks/s) +host_mem_usage 436668 # Number of bytes of host memory used +host_seconds 749.88 # Real time elapsed on the host +sim_insts 63030433 # Number of instructions simulated +sim_ops 75898814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 670652 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 5012160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 503736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 5163008 # Number of bytes read from this memory -system.physmem.bytes_read::total 134034100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 219584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 281408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4338816 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 674300 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 5028416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 495096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5148352 # Number of bytes read from this memory +system.physmem.bytes_read::total 134030836 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 219456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 280832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4344000 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7367952 # Number of bytes written to this memory +system.physmem.bytes_written::total 7373136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 78315 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 80672 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15512856 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 67794 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 78569 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 80443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 67875 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 825078 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46147592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 120 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 825159 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46147806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 96 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 252267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1885334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 189481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 1942075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50417182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 23255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 105852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1632054 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 253640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1891457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 186232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 1936571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50416189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82549 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 23087 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 105636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1634011 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 1133021 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2771469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1632054 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46147592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 1133026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2773432 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1634011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46147806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 96 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 258662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1885334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1322502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 1942075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53188651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15512856 # Number of read requests accepted -system.physmem.writeReqs 825078 # Number of write requests accepted -system.physmem.readBursts 15512856 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 825078 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992706816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 115968 # Total number of bytes read from write queue -system.physmem.bytesWritten 7383872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134034100 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7367952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1812 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709689 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15707 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 969471 # Per bank write bursts -system.physmem.perBankRdBursts::1 969246 # Per bank write bursts -system.physmem.perBankRdBursts::2 969043 # Per bank write bursts -system.physmem.perBankRdBursts::3 969564 # Per bank write bursts -system.physmem.perBankRdBursts::4 971813 # Per bank write bursts -system.physmem.perBankRdBursts::5 969510 # Per bank write bursts -system.physmem.perBankRdBursts::6 969103 # Per bank write bursts -system.physmem.perBankRdBursts::7 968972 # Per bank write bursts -system.physmem.perBankRdBursts::8 969597 # Per bank write bursts -system.physmem.perBankRdBursts::9 969588 # Per bank write bursts -system.physmem.perBankRdBursts::10 969467 # Per bank write bursts -system.physmem.perBankRdBursts::11 968939 # Per bank write bursts -system.physmem.perBankRdBursts::12 969138 # Per bank write bursts -system.physmem.perBankRdBursts::13 969444 # Per bank write bursts -system.physmem.perBankRdBursts::14 969295 # Per bank write bursts -system.physmem.perBankRdBursts::15 968854 # Per bank write bursts -system.physmem.perBankWrBursts::0 7363 # Per bank write bursts -system.physmem.perBankWrBursts::1 7345 # Per bank write bursts -system.physmem.perBankWrBursts::2 6989 # Per bank write bursts -system.physmem.perBankWrBursts::3 7254 # Per bank write bursts -system.physmem.perBankWrBursts::4 7419 # Per bank write bursts -system.physmem.perBankWrBursts::5 7425 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 260035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1891457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1319258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 1936571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53189621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15512805 # Number of read requests accepted +system.physmem.writeReqs 825159 # Number of write requests accepted +system.physmem.readBursts 15512805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 825159 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 992712960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 106560 # Total number of bytes read from write queue +system.physmem.bytesWritten 7389248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134030836 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7373136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1665 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709677 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 969393 # Per bank write bursts +system.physmem.perBankRdBursts::1 969270 # Per bank write bursts +system.physmem.perBankRdBursts::2 969024 # Per bank write bursts +system.physmem.perBankRdBursts::3 969581 # Per bank write bursts +system.physmem.perBankRdBursts::4 971912 # Per bank write bursts +system.physmem.perBankRdBursts::5 969565 # Per bank write bursts +system.physmem.perBankRdBursts::6 969152 # Per bank write bursts +system.physmem.perBankRdBursts::7 969036 # Per bank write bursts +system.physmem.perBankRdBursts::8 969555 # Per bank write bursts +system.physmem.perBankRdBursts::9 969606 # Per bank write bursts +system.physmem.perBankRdBursts::10 969469 # Per bank write bursts +system.physmem.perBankRdBursts::11 968910 # Per bank write bursts +system.physmem.perBankRdBursts::12 969137 # Per bank write bursts +system.physmem.perBankRdBursts::13 969414 # Per bank write bursts +system.physmem.perBankRdBursts::14 969294 # Per bank write bursts +system.physmem.perBankRdBursts::15 968822 # Per bank write bursts +system.physmem.perBankWrBursts::0 7303 # Per bank write bursts +system.physmem.perBankWrBursts::1 7359 # Per bank write bursts +system.physmem.perBankWrBursts::2 6981 # Per bank write bursts +system.physmem.perBankWrBursts::3 7260 # Per bank write bursts +system.physmem.perBankWrBursts::4 7486 # Per bank write bursts +system.physmem.perBankWrBursts::5 7442 # Per bank write bursts system.physmem.perBankWrBursts::6 7374 # Per bank write bursts -system.physmem.perBankWrBursts::7 7152 # Per bank write bursts -system.physmem.perBankWrBursts::8 7408 # Per bank write bursts -system.physmem.perBankWrBursts::9 7360 # Per bank write bursts -system.physmem.perBankWrBursts::10 7357 # Per bank write bursts -system.physmem.perBankWrBursts::11 7062 # Per bank write bursts -system.physmem.perBankWrBursts::12 6947 # Per bank write bursts -system.physmem.perBankWrBursts::13 7077 # Per bank write bursts -system.physmem.perBankWrBursts::14 7057 # Per bank write bursts -system.physmem.perBankWrBursts::15 6784 # Per bank write bursts +system.physmem.perBankWrBursts::7 7195 # Per bank write bursts +system.physmem.perBankWrBursts::8 7413 # Per bank write bursts +system.physmem.perBankWrBursts::9 7378 # Per bank write bursts +system.physmem.perBankWrBursts::10 7327 # Per bank write bursts +system.physmem.perBankWrBursts::11 7067 # Per bank write bursts +system.physmem.perBankWrBursts::12 6951 # Per bank write bursts +system.physmem.perBankWrBursts::13 7051 # Per bank write bursts +system.physmem.perBankWrBursts::14 7072 # Per bank write bursts +system.physmem.perBankWrBursts::15 6798 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2658500409000 # Total gap between requests +system.physmem.totGap 2658486560500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) system.physmem.readPktSize::3 15335449 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 177348 # Read request sizes (log2) +system.physmem.readPktSize::6 177297 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 67794 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1046196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1019688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 986842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1094338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 993106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1055542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2738032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2641383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3439999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 110050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 101603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67875 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1046149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1019751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 986849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1098941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 993476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1059379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2733951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2632980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3427107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 133098 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 114256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 105608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 102115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see @@ -180,32 +176,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -229,54 +225,55 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1037696 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 963.760762 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 885.523874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 219.463963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 32040 3.09% 3.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21332 2.06% 5.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9404 0.91% 6.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2470 0.24% 6.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3075 0.30% 6.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2164 0.21% 6.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8825 0.85% 7.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1075 0.10% 7.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 957311 92.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1037696 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6640 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2336.000602 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 97357.467769 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6632 99.88% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 3 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6640 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6640 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.375452 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.330517 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.281391 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2518 37.92% 37.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 36 0.54% 38.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3683 55.47% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 190 2.86% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 92 1.39% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 40 0.60% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 30 0.45% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.30% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 15 0.23% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 13 0.20% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 1037609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.852673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 885.641044 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 219.370096 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 32112 3.09% 3.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21277 2.05% 5.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9254 0.89% 6.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2543 0.25% 6.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3048 0.29% 6.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2181 0.21% 6.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8654 0.83% 7.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1069 0.10% 7.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957471 92.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1037609 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6645 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2334.257336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 73724.534105 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6636 99.86% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4.71859e+06-4.98074e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6645 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6645 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.375019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.329909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.281758 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2539 38.21% 38.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 27 0.41% 38.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3660 55.08% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 195 2.93% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 85 1.28% 97.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 0.86% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 40 0.60% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.17% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 9 0.14% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6640 # Writes before turning the bus around for reads -system.physmem.totQLat 403478953250 # Total ticks spent queuing -system.physmem.totMemAccLat 694311028250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77555220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26012.37 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6645 # Writes before turning the bus around for reads +system.physmem.totQLat 404032545000 # Total ticks spent queuing +system.physmem.totMemAccLat 694866420000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77555700000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26047.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44762.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44797.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s @@ -285,18 +282,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.94 # Data bus utilization in percentage system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.23 # Average write queue length when enqueuing -system.physmem.readRowHits 14503444 # Number of row buffer hits during reads -system.physmem.writeRowHits 85277 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.34 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 14503540 # Number of row buffer hits during reads +system.physmem.writeRowHits 85448 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.90 # Row buffer hit rate for writes -system.physmem.avgGap 162719.50 # Average gap between requests +system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes +system.physmem.avgGap 162718.35 # Average gap between requests system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2316371594000 # Time in different power states -system.physmem.memoryStateTime::REF 88773100000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2316452257000 # Time in different power states +system.physmem.memoryStateTime::REF 88772580000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 253353834750 # Time in different power states +system.physmem.memoryStateTime::ACT 253258119250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory @@ -316,498 +313,475 @@ system.realview.nvmem.bw_inst_read::total 265 # I system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16692425 # Transaction distribution -system.membus.trans_dist::ReadResp 16692425 # Transaction distribution -system.membus.trans_dist::WriteReq 768873 # Transaction distribution -system.membus.trans_dist::WriteResp 768873 # Transaction distribution -system.membus.trans_dist::Writeback 67794 # Transaction distribution -system.membus.trans_dist::UpgradeReq 55379 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 22285 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15707 # Transaction distribution -system.membus.trans_dist::ReadExReq 15268 # Transaction distribution +system.membus.trans_dist::ReadReq 16692376 # Transaction distribution +system.membus.trans_dist::ReadResp 16692376 # Transaction distribution +system.membus.trans_dist::WriteReq 768869 # Transaction distribution +system.membus.trans_dist::WriteResp 768869 # Transaction distribution +system.membus.trans_dist::Writeback 67875 # Transaction distribution +system.membus.trans_dist::UpgradeReq 55188 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 22300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15674 # Transaction distribution +system.membus.trans_dist::ReadExReq 15293 # Transaction distribution system.membus.trans_dist::ReadExResp 8420 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384484 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12552 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4436601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4436392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35107449 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35107240 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392912 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25104 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718660 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21141576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18720580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21143488 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 143824968 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 68805 # Total snoops (count) -system.membus.snoop_fanout::samples 327203 # Request fanout histogram +system.membus.pkt_size::total 143826880 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 68687 # Total snoops (count) +system.membus.snoop_fanout::samples 327086 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 327203 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 327086 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 327203 # Request fanout histogram -system.membus.reqLayer0.occupancy 1769123496 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 327086 # Request fanout histogram +system.membus.reqLayer0.occupancy 1769125500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 10983499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11055000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1597500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1598500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17876588998 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17877285000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5004631688 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5004493562 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37937018429 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37922455685 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 92212 # number of replacements -system.l2c.tags.tagsinuse 55213.567741 # Cycle average of tags in use -system.l2c.tags.total_refs 396364 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 156868 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.526736 # Average number of references to valid blocks. +system.l2c.tags.replacements 92119 # number of replacements +system.l2c.tags.tagsinuse 55174.117162 # Cycle average of tags in use +system.l2c.tags.total_refs 396231 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156723 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.528225 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 8088.192516 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.706191 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029154 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2502.443827 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29448.913538 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.609197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.004438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2039.532288 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13124.136592 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.123416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000057 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 8029.027858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.830738 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029129 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2503.920237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29498.221526 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.298488 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2007.480710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13123.308478 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.122513 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000043 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.038184 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.449355 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000086 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.031121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.842492 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 53217 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 11430 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.038207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.450107 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000127 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.030632 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200246 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.841890 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 53228 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 11362 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 151 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4758 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 48307 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1757 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 9394 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.812027 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.174408 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5122526 # Number of tag accesses -system.l2c.tags.data_accesses 5122526 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 183 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 37 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 15214 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88074 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 233 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 19471 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76181 # number of ReadReq hits -system.l2c.ReadReq_hits::total 199443 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 215065 # number of Writeback hits -system.l2c.Writeback_hits::total 215065 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 3153 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 2020 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5173 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 94 # number of SCUpgradeReq hits +system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4763 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 48327 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1719 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 9346 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.812195 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.173370 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5120698 # Number of tag accesses +system.l2c.tags.data_accesses 5120698 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 193 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 42 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 14931 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88016 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 59 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 19686 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76288 # number of ReadReq hits +system.l2c.ReadReq_hits::total 199452 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 215010 # number of Writeback hits +system.l2c.Writeback_hits::total 215010 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 3051 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 2025 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 5076 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 100 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 2198 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 2398 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4596 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 37 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 17412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 88074 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 233 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21869 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 76181 # number of demand (read+write) hits -system.l2c.demand_hits::total 204039 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 183 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 37 # number of overall hits -system.l2c.overall_hits::cpu0.inst 17412 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 88074 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 233 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21869 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 76181 # number of overall hits -system.l2c.overall_hits::total 204039 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::total 313 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 2211 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 2397 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4608 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 193 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 42 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 17142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 88016 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 59 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 22083 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 76288 # number of demand (read+write) hits +system.l2c.demand_hits::total 204060 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 193 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 42 # number of overall hits +system.l2c.overall_hits::cpu0.inst 17142 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 88016 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 237 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 59 # number of overall hits +system.l2c.overall_hits::cpu1.inst 22083 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 76288 # number of overall hits +system.l2c.overall_hits::total 204060 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4198 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3275 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq misses -system.l2c.ReadReq_misses::total 166478 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 7866 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 5570 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13436 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 1047 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1097 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2144 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 3980 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 4567 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 8547 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 4222 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3178 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80451 # number of ReadReq misses +system.l2c.ReadReq_misses::total 166440 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 7948 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 5460 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13408 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 1046 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 1101 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2147 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 4019 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 4520 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 8539 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8178 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7842 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) misses -system.l2c.demand_misses::total 175025 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses +system.l2c.demand_misses::cpu0.inst 8241 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7698 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 80451 # number of demand (read+write) misses +system.l2c.demand_misses::total 174979 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8178 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 78315 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7842 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 80672 # number of overall misses -system.l2c.overall_misses::total 175025 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 332000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 8241 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 78569 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7698 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 80451 # number of overall misses +system.l2c.overall_misses::total 174979 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 256500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 326103000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 790750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 142500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 265072000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16470995078 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 13809412 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 6376729 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 20186141 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 656474 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 4281316 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4937790 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 283206167 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 338006954 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 621213121 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 332000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 326360000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1107250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 255357749 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 16477212323 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 13294932 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 6165736 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 19460668 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 621976 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 4504808 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 5126784 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 291276419 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 332394712 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 623671131 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 256500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 609309167 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 790750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 142500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 603078954 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17092208199 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 332000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 617636419 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1107250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 587752461 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17100883454 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 256500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 609309167 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 790750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 142500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 603078954 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17092208199 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 188 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 39 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 19412 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 166389 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 243 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 22746 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 156853 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 365921 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 215065 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 215065 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 11019 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 7590 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18609 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 1141 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 1310 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2451 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 6178 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 6965 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 13143 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 39 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 25590 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 166389 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 243 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 29711 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 156853 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 379064 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 39 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 25590 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 166389 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 243 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 29711 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 156853 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 379064 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.051282 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.216258 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.143981 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.454956 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.713858 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.733860 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.722016 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.917616 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.837405 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.874745 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.644221 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.655707 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.650308 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.051282 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.319578 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.263943 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.461729 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.051282 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.319578 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.263943 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.461729 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66400 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 617636419 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1107250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 587752461 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17100883454 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 197 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 44 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 19153 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 166585 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 251 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 59 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 22864 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 156739 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 365892 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 215010 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 215010 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 10999 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 7485 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18484 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 1146 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 1314 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2460 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 6230 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 6917 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 13147 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 197 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 44 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 25383 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 166585 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 251 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 59 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 29781 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 156739 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 379039 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 197 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 44 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 25383 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 166585 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 251 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 59 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 29781 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 156739 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 379039 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.045455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.220435 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.138996 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.454888 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.722611 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.729459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.725384 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.912740 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.837900 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.872764 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.645104 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.653462 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.649502 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.045455 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.324666 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.258487 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.461639 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.045455 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.324666 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.258487 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.461639 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 64125 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77680.562172 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79075 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 142500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80938.015267 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 98937.968248 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1755.582507 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1144.834650 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1502.392155 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 627.004776 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 3902.749316 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2303.073694 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 71157.328392 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74010.719072 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 72682.007839 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66400 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77299.857887 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80351.714600 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 98997.911097 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1672.739305 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1129.255678 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1451.422136 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 594.623327 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 4091.560400 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2387.882627 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 72474.849216 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73538.653097 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73037.958894 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 64125 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 74505.889826 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79075 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76903.717674 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 97655.810307 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66400 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 74946.780609 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76351.319953 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 97731.061750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 64125 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 74505.889826 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79075 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76903.717674 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 97655.810307 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 174 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 74946.780609 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76351.319953 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 97731.061750 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 255 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 34.800000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 42.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 67795 # number of writebacks -system.l2c.writebacks::total 67795 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 5 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 67875 # number of writebacks +system.l2c.writebacks::total 67875 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 10 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4198 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3274 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 166477 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 7866 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 5570 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 13436 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 1047 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1097 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2144 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 3980 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 4567 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 8547 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 5 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 4222 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3176 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 166430 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.inst 7948 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.inst 5460 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 13408 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 1046 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1101 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2147 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.inst 4019 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.inst 4520 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 8539 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8178 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 7841 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 175024 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 5 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8241 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 7696 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 174969 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8178 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 7841 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 175024 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 270000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 8241 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 7696 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 174969 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 207500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 273844500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 666250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 130500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 224380000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 14413044080 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 79216804 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 56126525 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 135343329 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 10623534 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 10994091 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 21617625 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 233127823 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 280625546 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 513753369 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 270000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 273765000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 936250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 215773749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 14418655831 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 80020888 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 54949416 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 134970304 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 10533533 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 11044096 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 21577629 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 240707081 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 275649788 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 516356869 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 207500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 506972323 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 666250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 130500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 505005546 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 14926797449 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 270000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 514472081 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 936250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 491423537 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 14935012700 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 207500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 506972323 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 666250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 130500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 505005546 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 14926797449 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12572348996 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155062093246 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167634442242 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125655500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721437217 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16847092717 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13698004496 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170783530463 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184481534959 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.216258 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.143937 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.454953 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.713858 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.733860 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.722016 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.917616 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837405 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.874745 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.644221 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.655707 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.650308 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.461727 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.461727 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 514472081 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 936250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 491423537 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 14935012700 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12573700750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155061349748 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167635050498 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125597500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721355858 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16846953358 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13699298250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170782705606 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184482003856 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.220435 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.454861 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.722611 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.729459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.725384 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.912740 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837900 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.872764 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.645104 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.653462 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.649502 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.461612 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.461612 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65232.134350 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68533.903482 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 86576.788866 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.786168 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.575404 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10073.186142 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10146.641834 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10021.960802 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10082.847481 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 58574.829899 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61446.364353 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60109.204282 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64842.491710 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67938.837846 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 86634.956624 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10068.053347 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10063.995604 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.400955 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.299235 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10030.968211 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10050.129949 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 59892.281911 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60984.466372 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60470.414451 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -824,48 +798,48 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 1655769 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1655769 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 768873 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 768873 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 215065 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60425 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 22592 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 83017 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 22828 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 22828 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 802487 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302639 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5105126 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20032432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23601176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 43633608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 171019 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 786212 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1655552 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1655552 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 768869 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 768869 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 215010 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60145 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 22613 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 82758 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 22833 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 22833 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 801778 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302678 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5104456 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20000696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23627528 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 43628224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 170698 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 785697 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 786212 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 785697 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 786212 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2618569936 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 785697 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2618065998 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1234710374 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1234480729 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2607103376 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2606264414 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16519576 # Transaction distribution -system.iobus.trans_dist::ReadResp 16519576 # Transaction distribution +system.iobus.trans_dist::ReadReq 16519582 # Transaction distribution +system.iobus.trans_dist::ReadResp 16519582 # Transaction distribution system.iobus.trans_dist::WriteReq 8084 # Transaction distribution system.iobus.trans_dist::WriteResp 8084 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -887,12 +861,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384484 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33055320 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33055332 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17880 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -914,13 +888,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2392888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 125076280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 125076304 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4470000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4476000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -966,19 +940,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376388000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376400000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38667942571 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38686704315 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7247667 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5145194 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 425040 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4677323 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3357189 # Number of BTB hits +system.cpu0.branchPred.lookups 7252165 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5142285 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 425056 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4634449 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3350199 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.775864 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 942424 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 64273 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.289047 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 946301 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 66428 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1002,25 +976,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6449421 # DTB read hits -system.cpu0.dtb.read_misses 22629 # DTB read misses -system.cpu0.dtb.write_hits 5803237 # DTB write hits -system.cpu0.dtb.write_misses 1880 # DTB write misses +system.cpu0.dtb.read_hits 6449087 # DTB read hits +system.cpu0.dtb.read_misses 22394 # DTB read misses +system.cpu0.dtb.write_hits 5803603 # DTB write hits +system.cpu0.dtb.write_misses 1784 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1731 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1649 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 155 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1724 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1623 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 268 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6472050 # DTB read accesses -system.cpu0.dtb.write_accesses 5805117 # DTB write accesses +system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6471481 # DTB read accesses +system.cpu0.dtb.write_accesses 5805387 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12252658 # DTB hits -system.cpu0.dtb.misses 24509 # DTB misses -system.cpu0.dtb.accesses 12277167 # DTB accesses +system.cpu0.dtb.hits 12252690 # DTB hits +system.cpu0.dtb.misses 24178 # DTB misses +system.cpu0.dtb.accesses 12276868 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1042,8 +1016,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 13306402 # ITB inst hits -system.cpu0.itb.inst_misses 3981 # ITB inst misses +system.cpu0.itb.inst_hits 13302311 # ITB inst hits +system.cpu0.itb.inst_misses 3954 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1052,83 +1026,83 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1196 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1195 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 3606 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 3570 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 13310383 # ITB inst accesses -system.cpu0.itb.hits 13306402 # DTB hits -system.cpu0.itb.misses 3981 # DTB misses -system.cpu0.itb.accesses 13310383 # DTB accesses -system.cpu0.numCycles 86779776 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 13306265 # ITB inst accesses +system.cpu0.itb.hits 13302311 # DTB hits +system.cpu0.itb.misses 3954 # DTB misses +system.cpu0.itb.accesses 13306265 # DTB accesses +system.cpu0.numCycles 86799146 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29469177 # Number of instructions committed -system.cpu0.committedOps 35692469 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 1968048 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 41085 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5234632408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.944764 # CPI: cycles per instruction -system.cpu0.ipc 0.339586 # IPC: instructions per cycle +system.cpu0.committedInsts 29471412 # Number of instructions committed +system.cpu0.committedOps 35693999 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 1972340 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 41075 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5234564326 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.945198 # CPI: cycles per instruction +system.cpu0.ipc 0.339536 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 47499 # number of quiesce instructions executed -system.cpu0.tickCycles 68210329 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 18569447 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 669895 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.780265 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 12632215 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 670407 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.842606 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6077782000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780265 # Average occupied blocks per requestor +system.cpu0.kern.inst.quiesce 47489 # number of quiesce instructions executed +system.cpu0.tickCycles 68192545 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 18606601 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 670908 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.780495 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 12627162 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 671420 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.806652 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6076833000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780495 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 27275662 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 27275662 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 12632215 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 12632215 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 12632215 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 12632215 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 12632215 # number of overall hits -system.cpu0.icache.overall_hits::total 12632215 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 670411 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 670411 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 670411 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 670411 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 670411 # number of overall misses -system.cpu0.icache.overall_misses::total 670411 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5588337897 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5588337897 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5588337897 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5588337897 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5588337897 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5588337897 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 13302626 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 13302626 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 13302626 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 13302626 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 13302626 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 13302626 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050397 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050397 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050397 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050397 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050397 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050397 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8335.689446 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8335.689446 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8335.689446 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8335.689446 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 27268595 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 27268595 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 12627162 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 12627162 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 12627162 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 12627162 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 12627162 # number of overall hits +system.cpu0.icache.overall_hits::total 12627162 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 671424 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 671424 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 671424 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 671424 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 671424 # number of overall misses +system.cpu0.icache.overall_misses::total 671424 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5600052378 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5600052378 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5600052378 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5600052378 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5600052378 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5600052378 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 13298586 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 13298586 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 13298586 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 13298586 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 13298586 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 13298586 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050488 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050488 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050488 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050488 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050488 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050488 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8340.560328 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8340.560328 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8340.560328 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8340.560328 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1137,365 +1111,375 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 670411 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 670411 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 670411 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 670411 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 670411 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 670411 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4581839103 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4581839103 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4581839103 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4581839103 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4581839103 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4581839103 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 215199250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 215199250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 215199250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 215199250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050397 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050397 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050397 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6834.373396 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 671424 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 671424 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 671424 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 671424 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 671424 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 671424 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4592017122 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4592017122 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4592017122 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4592017122 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4592017122 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4592017122 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 214843000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 214843000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 214843000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 214843000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050488 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050488 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050488 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6839.221002 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1297449 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1098949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 10915 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 10915 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 277394 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 309853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 48681 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 54656 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 145161 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 136933 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1345495 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1384854 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13521 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 67392 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 2811262 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43053120 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45712112 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22348 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 121316 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 88908896 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 663093 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2014813 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.294791 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.455949 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1296970 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1098887 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 10913 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 10913 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 275708 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 308200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 48588 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23370 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 54742 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 144812 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 136646 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1347493 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1381165 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13298 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 66487 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 2808443 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43116416 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45547448 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21688 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119336 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 88804888 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 661783 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2010538 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.294459 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.455799 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 1420865 70.52% 70.52% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 593948 29.48% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 1418517 70.55% 70.55% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 592021 29.45% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2014813 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1042501632 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2010538 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1039622669 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 66915000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 67426500 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1010138647 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1011659878 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 706064108 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 704346240 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7935497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7877498 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 37067990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 36655495 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6505286 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 197873 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6075585 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2087 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6510276 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 198706 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6081219 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2295 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 227641 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 451994 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2119 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 225934 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 452636 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 185568 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16045.943959 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1211197 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 201780 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.002562 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5120960000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4785.288649 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 15.661304 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.175022 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2150.935803 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9093.883182 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.292071 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000956 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000011 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.131283 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.555047 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.979367 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8308 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7886 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 36 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 61 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 933 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5734 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1544 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1527 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5465 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 648 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.507080 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.481323 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 22965812 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 22965812 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29822 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5414 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 885726 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 920962 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 277394 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 277394 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1852 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1852 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 771 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 771 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107990 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 107990 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29822 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5414 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 993716 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1028952 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29822 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5414 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 993716 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1028952 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 507 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49350 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 50030 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18889 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 18889 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10120 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 10120 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23685 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 23685 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 507 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 73035 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 73715 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 507 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 73035 # number of overall misses -system.cpu0.l2cache.overall_misses::total 73715 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10873500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3613500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1326942681 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1341429681 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312233020 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 312233020 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 200699599 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 200699599 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1269500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1269500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 847496588 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 847496588 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10873500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3613500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2174439269 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 2188926269 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10873500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3613500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2174439269 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 2188926269 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 30329 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5587 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935076 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 970992 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 277394 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 277394 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20741 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 20741 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10891 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 10891 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131675 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 131675 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 30329 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5587 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1066751 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1102667 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 30329 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5587 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1066751 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1102667 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030965 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052776 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.051525 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.910708 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.910708 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.929208 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.929208 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179875 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179875 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030965 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068465 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.066852 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030965 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068465 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.066852 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 20887.283237 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26888.402857 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26812.506116 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16529.886177 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16529.886177 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19831.976186 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19831.976186 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 35781.996538 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35781.996538 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 20887.283237 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29772.564784 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 29694.448470 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 20887.283237 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29772.564784 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 29694.448470 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 1346 # number of cycles access was blocked +system.cpu0.l2cache.tags.replacements 185629 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16039.205043 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1209112 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 201843 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.990359 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5120294500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4761.005363 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.831562 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.161164 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2118.524351 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9136.682602 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.290589 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001394 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.129304 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.557659 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.978955 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8350 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7848 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 57 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 864 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5964 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1431 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1438 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5471 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509644 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.479004 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 22924468 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 22924468 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29315 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5251 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 886043 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 920609 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 275708 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 275708 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1811 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 1811 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 729 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 729 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107812 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 107812 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29315 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5251 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 993855 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1028421 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29315 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5251 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 993855 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1028421 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 519 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49158 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 49848 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18945 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 18945 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10134 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 10134 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23532 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 23532 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 519 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 72690 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 73380 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 519 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 72690 # number of overall misses +system.cpu0.l2cache.overall_misses::total 73380 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11037500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618999 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1323798925 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1338455424 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312100526 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 312100526 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 201024600 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 201024600 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1393500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1393500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 857324396 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 857324396 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11037500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618999 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2181123321 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 2195779820 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11037500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618999 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2181123321 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 2195779820 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 29834 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5422 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935201 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 970457 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 275708 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 275708 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20756 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 20756 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10863 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 10863 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131344 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 131344 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 29834 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5422 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1066545 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1101801 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 29834 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5422 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1066545 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1101801 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031538 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052564 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.051365 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.912748 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.912748 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.932891 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.932891 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179163 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179163 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031538 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068155 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.066600 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031538 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068155 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.066600 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21163.736842 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26929.470788 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26850.734714 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16474.031459 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16474.031459 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19836.648905 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19836.648905 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 232250 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 232250 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 36432.279279 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 36432.279279 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 29923.409921 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 29923.409921 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 39.588235 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 24.300000 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 114944 # number of writebacks -system.cpu0.l2cache.writebacks::total 114944 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2945 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 2945 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 748 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 748 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3693 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3693 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3693 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3693 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 507 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 46405 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 47085 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 227640 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 227640 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 18889 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18889 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 10120 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10120 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 22937 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 22937 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 507 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69342 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 70022 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 507 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69342 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 227640 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 297662 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2402500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 949940475 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 959667475 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8587835748 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 341053600 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 341053600 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 145849953 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 145849953 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1059500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1059500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 592786901 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 592786901 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2402500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1542727376 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 1552454376 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2402500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1542727376 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 10140290124 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14160332496 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14160332496 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312896000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312896000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15473228496 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15473228496 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.049627 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.048492 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 114449 # number of writebacks +system.cpu0.l2cache.writebacks::total 114449 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2940 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 2940 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 800 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 800 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3740 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3740 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3740 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3740 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 519 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 171 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 46218 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 46908 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 225933 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 225933 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 18945 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18945 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 10134 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10134 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 6 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 22732 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 22732 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 519 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 171 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 68950 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 69640 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 519 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 171 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 68950 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 225933 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 295573 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2421001 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 946752983 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 956578484 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8634543726 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8634543726 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 342474562 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 342474562 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 146006456 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 146006456 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1155500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1155500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 598541592 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 598541592 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2421001 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1545294575 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 1555120076 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2421001 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1545294575 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8634543726 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 10189663802 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14161707249 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14161707249 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312859997 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312859997 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15474567246 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15474567246 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.049420 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.048336 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.910708 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.910708 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.929208 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.929208 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.174194 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.174194 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.065003 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063502 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.065003 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.912748 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.912748 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.932891 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.932891 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.173072 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.173072 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063206 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.269947 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20470.649176 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20381.596581 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37725.512862 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18055.672614 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18055.672614 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14412.050692 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14412.050692 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 25844.133976 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25844.133976 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22170.951644 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34066.458345 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.268264 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20484.507832 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20392.651232 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 38217.275591 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18077.305991 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18077.305991 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14407.583975 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14407.583975 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 192583.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192583.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 26330.353335 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26330.353335 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22330.845434 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34474.271337 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1503,99 +1487,99 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 363620 # number of replacements -system.cpu0.dcache.tags.tagsinuse 473.092728 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11412864 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 364132 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.342656 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 362294 # number of replacements +system.cpu0.dcache.tags.tagsinuse 472.891448 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11414416 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 362806 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.461486 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.092728 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924009 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.924009 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 472.891448 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.923616 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.923616 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 24359055 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 24359055 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 5804369 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5804369 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275244 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5275244 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147463 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147463 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146615 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146615 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 11079613 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11079613 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 11079613 # number of overall hits -system.cpu0.dcache.overall_hits::total 11079613 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 309599 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 309599 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 276951 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 276951 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10168 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10168 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10891 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10891 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 586550 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 586550 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 586550 # number of overall misses -system.cpu0.dcache.overall_misses::total 586550 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3701357617 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3701357617 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4193199790 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4193199790 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 166675501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 166675501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254636964 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 254636964 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1359500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1359500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 7894557407 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7894557407 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 7894557407 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7894557407 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113968 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6113968 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5552195 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5552195 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157631 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157631 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157506 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157506 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 11666163 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11666163 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 11666163 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11666163 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050638 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.050638 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049881 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049881 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064505 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064505 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069147 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069147 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050278 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.050278 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050278 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.050278 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11955.328076 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11955.328076 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15140.583677 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15140.583677 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16392.161782 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16392.161782 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23380.494353 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23380.494353 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 24357333 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 24357333 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 5805631 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5805631 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275579 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275579 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147422 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147422 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146630 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146630 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 11081210 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11081210 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 11081210 # number of overall hits +system.cpu0.dcache.overall_hits::total 11081210 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 308329 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 308329 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 276386 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 276386 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10191 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10191 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10869 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 10869 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 584715 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 584715 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 584715 # number of overall misses +system.cpu0.dcache.overall_misses::total 584715 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3680932639 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3680932639 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4210104069 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4210104069 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 167480751 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 167480751 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254581965 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 254581965 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1495500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1495500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 7891036708 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7891036708 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 7891036708 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7891036708 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113960 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6113960 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5551965 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5551965 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157499 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157499 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 11665925 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11665925 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 11665925 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11665925 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050430 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.050430 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049782 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049782 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064658 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064658 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050122 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.050122 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050122 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.050122 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11938.327692 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11938.327692 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15232.696551 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15232.696551 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16434.182220 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16434.182220 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23422.758763 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23422.758763 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13459.308511 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13459.308511 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13495.526381 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13495.526381 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1604,76 +1588,76 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 277395 # number of writebacks -system.cpu0.dcache.writebacks::total 277395 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54934 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 54934 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124546 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 124546 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 275708 # number of writebacks +system.cpu0.dcache.writebacks::total 275708 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54553 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 54553 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124298 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 124298 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 179480 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 179480 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 179480 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 179480 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 254665 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 254665 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152405 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 152405 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10094 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10094 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10891 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10891 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 407070 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 407070 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 407070 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 407070 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2527058296 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2527058296 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2131958823 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2131958823 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 145779499 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145779499 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231881036 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231881036 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1299500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1299500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4659017119 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4659017119 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4659017119 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4659017119 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14650509239 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14650509239 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394876998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394876998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16045386237 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16045386237 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041653 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041653 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027450 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027450 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069147 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069147 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034893 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.034893 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9923.068722 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9923.068722 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13988.772173 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13988.772173 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14442.193283 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14442.193283 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21291.069323 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21291.069323 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 178851 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 178851 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 178851 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 178851 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 253776 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 253776 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152088 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 152088 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10117 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10117 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10869 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10869 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 405864 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 405864 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 405864 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 405864 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2514607539 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2514607539 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2141849701 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2141849701 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 146522249 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146522249 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231876035 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231876035 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1427500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1427500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4656457240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4656457240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4656457240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4656457240 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14652229736 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14652229736 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394826498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394826498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16047056234 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16047056234 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041508 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041508 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027394 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027394 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064189 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064189 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034791 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034791 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9908.768122 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9908.768122 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14082.963159 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14082.963159 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14482.776416 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14482.776416 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21333.704573 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21333.704573 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1681,15 +1665,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7015971 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5101339 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 682515 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5021553 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3808301 # Number of BTB hits +system.cpu1.branchPred.lookups 7012649 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5102138 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 681212 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4956162 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3806104 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 75.839108 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 855690 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 72942 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 76.795391 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 854817 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 71801 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1713,25 +1697,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7897430 # DTB read hits -system.cpu1.dtb.read_misses 21135 # DTB read misses -system.cpu1.dtb.write_hits 6047519 # DTB write hits -system.cpu1.dtb.write_misses 2176 # DTB write misses +system.cpu1.dtb.read_hits 7899300 # DTB read hits +system.cpu1.dtb.read_misses 20789 # DTB read misses +system.cpu1.dtb.write_hits 6047693 # DTB write hits +system.cpu1.dtb.write_misses 2209 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3376 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1917 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3619 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7918565 # DTB read accesses -system.cpu1.dtb.write_accesses 6049695 # DTB write accesses +system.cpu1.dtb.perms_faults 329 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7920089 # DTB read accesses +system.cpu1.dtb.write_accesses 6049902 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13944949 # DTB hits -system.cpu1.dtb.misses 23311 # DTB misses -system.cpu1.dtb.accesses 13968260 # DTB accesses +system.cpu1.dtb.hits 13946993 # DTB hits +system.cpu1.dtb.misses 22998 # DTB misses +system.cpu1.dtb.accesses 13969991 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1753,8 +1737,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 14225149 # ITB inst hits -system.cpu1.itb.inst_misses 5020 # ITB inst misses +system.cpu1.itb.inst_hits 14215184 # ITB inst hits +system.cpu1.itb.inst_misses 5010 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1763,81 +1747,81 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1294 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1291 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 3363 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 3360 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 14230169 # ITB inst accesses -system.cpu1.itb.hits 14225149 # DTB hits -system.cpu1.itb.misses 5020 # DTB misses -system.cpu1.itb.accesses 14230169 # DTB accesses -system.cpu1.numCycles 502333604 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 14220194 # ITB inst accesses +system.cpu1.itb.hits 14215184 # DTB hits +system.cpu1.itb.misses 5010 # DTB misses +system.cpu1.itb.accesses 14220194 # DTB accesses +system.cpu1.numCycles 502294457 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 33559332 # Number of instructions committed -system.cpu1.committedOps 40204034 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 2027525 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 40422 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 4816582490 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 14.968522 # CPI: cycles per instruction -system.cpu1.ipc 0.066807 # IPC: instructions per cycle +system.cpu1.committedInsts 33559021 # Number of instructions committed +system.cpu1.committedOps 40204815 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 2028180 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 40425 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 4816571571 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 14.967494 # CPI: cycles per instruction +system.cpu1.ipc 0.066811 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 45430 # number of quiesce instructions executed -system.cpu1.tickCycles 438569606 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 63763998 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 776883 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.132911 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13444222 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 777395 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 17.293939 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 68940011500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.132911 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974869 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974869 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 45433 # number of quiesce instructions executed +system.cpu1.tickCycles 438597056 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 63697401 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 777492 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.131548 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13433657 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 778004 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 17.266823 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 71929000500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.131548 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974866 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974866 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 29220629 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 29220629 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13444222 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13444222 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13444222 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13444222 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13444222 # number of overall hits -system.cpu1.icache.overall_hits::total 13444222 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 777395 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 777395 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 777395 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 777395 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 777395 # number of overall misses -system.cpu1.icache.overall_misses::total 777395 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6473834509 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6473834509 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6473834509 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6473834509 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6473834509 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6473834509 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 14221617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 14221617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 14221617 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 14221617 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 14221617 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 14221617 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054663 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.054663 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054663 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.054663 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054663 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.054663 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8327.599880 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8327.599880 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8327.599880 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8327.599880 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 29201326 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 29201326 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13433657 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13433657 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13433657 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13433657 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13433657 # number of overall hits +system.cpu1.icache.overall_hits::total 13433657 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 778004 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 778004 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 778004 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 778004 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 778004 # number of overall misses +system.cpu1.icache.overall_misses::total 778004 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6472911750 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6472911750 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6472911750 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6472911750 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6472911750 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6472911750 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 14211661 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 14211661 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 14211661 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 14211661 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 14211661 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 14211661 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054744 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.054744 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054744 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.054744 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054744 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.054744 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8319.895206 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8319.895206 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8319.895206 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8319.895206 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1846,371 +1830,370 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 777395 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 777395 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 777395 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 777395 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 777395 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 777395 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5306001991 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5306001991 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5306001991 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5306001991 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5306001991 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5306001991 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7443500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7443500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7443500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7443500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054663 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.054663 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.054663 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6825.361613 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 778004 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 778004 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 778004 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 778004 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 778004 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 778004 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5304159248 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5304159248 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5304159248 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5304159248 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5304159248 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5304159248 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7302500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7302500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7302500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 7302500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054744 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.054744 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.054744 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6817.650357 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 2372884 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 2161619 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 757958 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 757958 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 242023 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 269237 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 52848 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23732 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 50462 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 145739 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 137938 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1554692 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4766762 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17488 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67601 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 6406543 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49741696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44501144 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30140 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 121260 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94394240 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 607829 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2003123 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.277710 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.447870 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 2373135 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 2161912 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 757956 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 757956 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 242084 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 267987 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 52917 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23794 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 50912 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 145700 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 137856 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1555984 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4768118 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17545 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 6408081 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49785408 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44521800 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119152 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94456776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 606235 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2002284 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.277104 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.447568 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1446836 72.23% 72.23% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 556287 27.77% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1447444 72.29% 72.29% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 554840 27.71% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2003123 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2275243689 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2002284 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2275579743 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 46353997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 46369000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1167104009 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1168020751 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 2025335762 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 2025918980 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9955994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9945491 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 37292239 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 36649244 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6843055 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163843 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6478033 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2741 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6850018 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163294 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6486593 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2687 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2015 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 196423 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 563857 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2014 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 195430 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564382 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 179577 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15624.309787 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1195829 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 195022 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.131765 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2581358397500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4477.438103 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.594175 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.081575 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2724.649779 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8398.546154 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.273281 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001379 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000066 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.166299 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.512607 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.953632 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9457 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5975 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2071 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1611 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5775 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2329 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 929 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2717 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.577209 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364685 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 23391503 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 23391503 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29831 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7391 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 925413 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 962635 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 242023 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 242023 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1118 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1118 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112181 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 112181 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29831 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7391 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1037594 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1074816 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29831 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7391 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1037594 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1074816 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 484 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 144 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61489 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 62117 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18553 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 18553 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12524 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 12524 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 24216 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 24216 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 484 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 144 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 85705 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 86333 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 484 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 144 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 85705 # number of overall misses -system.cpu1.l2cache.overall_misses::total 86333 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10993750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3129500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1532483424 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1546606674 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 310148223 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 310148223 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 250854673 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 250854673 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 743500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 743500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1014040211 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1014040211 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10993750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3129500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2546523635 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2560646885 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10993750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3129500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2546523635 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2560646885 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30315 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7535 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 986902 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1024752 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 242023 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 242023 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20363 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 20363 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13642 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 13642 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136397 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 136397 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30315 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7535 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1123299 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1161149 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30315 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7535 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1123299 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1161149 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019111 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062305 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.060617 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.911113 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.911113 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.918047 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.918047 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 179644 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15634.197458 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1195685 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 195044 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.130335 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2581359096500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4491.320198 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.341759 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.933743 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.115946 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8353.485812 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.274128 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001425 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168708 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.509856 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.954236 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9491 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5898 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2061 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1580 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5850 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2269 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2711 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.579285 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359985 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 23405517 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 23405517 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29293 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7458 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 926354 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 963105 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 242084 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 242084 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1948 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1948 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1158 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1158 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112338 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 112338 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29293 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7458 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 1038692 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1075443 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29293 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7458 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 1038692 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1075443 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 495 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 146 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61595 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 62236 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18656 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 18656 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12530 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 12530 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 3 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 23997 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 23997 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 495 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 146 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 85592 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 86233 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 495 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 146 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 85592 # number of overall misses +system.cpu1.l2cache.overall_misses::total 86233 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11596750 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3042000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1525132928 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1539771678 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 312251712 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 312251712 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 251269185 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 251269185 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 836500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 836500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1004785618 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1004785618 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11596750 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3042000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2529918546 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2544557296 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11596750 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3042000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2529918546 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2544557296 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29788 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7604 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 987949 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1025341 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 242084 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 242084 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20604 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 20604 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13688 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 13688 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136335 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 136335 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29788 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7604 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 1124284 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1161676 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29788 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7604 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 1124284 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1161676 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019200 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062346 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.060698 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.905455 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.905455 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.915400 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.915400 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.177541 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.177541 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019111 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076298 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.074351 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019111 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076298 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.074351 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21732.638889 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 24922.887411 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24898.283465 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 16716.877217 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16716.877217 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20029.916401 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20029.916401 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 743500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 743500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41874.802238 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41874.802238 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21732.638889 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 29660.117047 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21732.638889 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 29660.117047 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 2162 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.176015 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.176015 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019200 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076130 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.074232 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019200 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076130 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.074232 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20835.616438 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 24760.661223 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24740.852208 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 16737.334477 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16737.334477 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20053.406624 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20053.406624 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 278833.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 278833.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41871.301329 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41871.301329 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20835.616438 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29557.885620 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 29507.929633 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20835.616438 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29557.885620 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 29507.929633 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 1374 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 53 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 40.792453 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24.981818 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 100121 # number of writebacks -system.cpu1.l2cache.writebacks::total 100121 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3717 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 3717 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 1346 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 1346 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5063 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 5063 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5063 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 5063 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 484 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 144 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 57772 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 58400 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 196422 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 196422 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 18553 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 18553 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 12524 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12524 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 22870 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 22870 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 484 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 144 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 80642 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 81270 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 484 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 144 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 80642 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 196422 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 277692 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2121500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1060116241 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1069841991 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10135528743 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 305752523 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 305752523 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 178428901 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 178428901 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 582500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 582500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 637234022 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 637234022 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2121500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1697350263 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 1707076013 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2121500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1697350263 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 11842604756 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174928342748 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174928342748 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797063287 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797063287 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203725406035 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 203725406035 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.058539 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.056989 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 100561 # number of writebacks +system.cpu1.l2cache.writebacks::total 100561 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3711 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 3711 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 1353 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 1353 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5064 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 5064 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5064 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 5064 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 495 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 146 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 57884 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 58525 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 195430 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 195430 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 18656 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 18656 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 12530 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12530 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 3 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 22644 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 22644 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 495 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 146 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 80528 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 81169 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 495 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 146 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 80528 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 195430 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 276599 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2020000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1052949978 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1063101228 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10102217802 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10102217802 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 306954055 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 306954055 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 178539396 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 178539396 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 654500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 654500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 627825362 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 627825362 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2020000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1680775340 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 1690926590 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2020000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1680775340 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10102217802 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 11793144392 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174927425750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174927425750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797119642 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797119642 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203724545392 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 203724545392 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.058590 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.057079 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.911113 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.911113 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.918047 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.918047 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.905455 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.905455 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.915400 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915400 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.167672 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.167672 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.071790 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.069991 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071790 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.166091 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.166091 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.069872 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.239153 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18350.000710 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18319.212175 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51600.781700 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16479.950574 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16479.950574 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14246.957921 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14246.957921 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 582500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 582500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27863.315348 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27863.315348 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21004.995853 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42646.546375 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.238103 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18190.691348 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18164.907783 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51692.257084 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16453.369157 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16453.369157 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14248.954190 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14248.954190 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 218166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 218166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27725.903639 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27725.903639 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20832.172258 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42636.251006 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2218,96 +2201,96 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 322636 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.144142 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11399665 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 322979 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.295375 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 72461169500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.144142 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959266 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959266 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24160845 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24160845 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 6375348 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6375348 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 4820943 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4820943 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 83445 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 83445 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 81578 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 81578 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 11196291 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11196291 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 11196291 # number of overall hits -system.cpu1.dcache.overall_hits::total 11196291 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 234523 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 234523 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 286003 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 286003 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 11843 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11843 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 13643 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 13643 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 520526 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 520526 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 520526 # number of overall misses -system.cpu1.dcache.overall_misses::total 520526 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3079569141 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3079569141 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 4582527620 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4582527620 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 211610249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 211610249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 314496917 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 314496917 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 813000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 813000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 7662096761 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7662096761 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 7662096761 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7662096761 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6609871 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6609871 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 5106946 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5106946 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 95288 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95288 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 95221 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95221 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 11716817 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11716817 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 11716817 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11716817 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.035481 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035481 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.056003 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.056003 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.124286 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124286 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.143277 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.143277 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044426 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044426 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044426 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044426 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 13131.203085 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13131.203085 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16022.655776 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16022.655776 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 17867.959892 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17867.959892 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23051.888661 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23051.888661 # average StoreCondReq miss latency +system.cpu1.dcache.tags.replacements 322748 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.331318 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11400815 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 323107 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.284952 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 72473667000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.331318 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959631 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.959631 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24164293 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24164293 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 6375660 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6375660 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 4821255 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4821255 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 83384 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 83384 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 81522 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 81522 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 11196915 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11196915 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 11196915 # number of overall hits +system.cpu1.dcache.overall_hits::total 11196915 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 235192 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 235192 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 286280 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 286280 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 11913 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11913 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 13691 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 13691 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 521472 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 521472 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 521472 # number of overall misses +system.cpu1.dcache.overall_misses::total 521472 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3078984138 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3078984138 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 4572469338 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4572469338 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 214431997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 214431997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 314961410 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 314961410 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 915000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 915000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 7651453476 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7651453476 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 7651453476 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7651453476 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6610852 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6610852 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 5107535 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5107535 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 95297 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95297 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 95213 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95213 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 11718387 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11718387 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 11718387 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11718387 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.035577 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035577 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.056051 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.056051 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.125009 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125009 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.143793 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.143793 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044500 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044500 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044500 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044500 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 13091.364239 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13091.364239 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15972.018087 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 15972.018087 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 17999.831864 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17999.831864 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23004.996713 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23004.996713 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14719.911707 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14719.911707 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14672.798302 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14672.798302 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2316,76 +2299,76 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 242023 # number of writebacks -system.cpu1.dcache.writebacks::total 242023 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36547 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 36547 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129246 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 129246 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 45 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 165793 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 165793 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 165793 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 165793 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 197976 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 197976 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156757 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 156757 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11798 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11798 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13643 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 13643 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 354733 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 354733 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 354733 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 354733 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204262298 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204262298 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2289972148 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2289972148 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 187457749 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 187457749 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286173083 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286173083 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 767000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 767000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4494234446 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4494234446 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4494234446 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4494234446 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183748244745 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183748244745 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481816713 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481816713 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218230061458 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218230061458 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029952 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029952 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030695 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030695 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.123814 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123814 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143277 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143277 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030276 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030276 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11133.987443 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11133.987443 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14608.420345 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14608.420345 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 15888.942956 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15888.942956 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20975.817855 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20975.817855 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 242084 # number of writebacks +system.cpu1.dcache.writebacks::total 242084 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36921 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 36921 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129344 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 129344 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 46 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 166265 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 166265 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 166265 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 166265 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 198271 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 198271 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156936 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 156936 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11867 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11867 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13691 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 13691 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 355207 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 355207 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 355207 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 355207 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202163297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202163297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2284592028 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2284592028 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 190117000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 190117000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286543590 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286543590 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 863000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 863000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4486755325 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4486755325 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4486755325 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4486755325 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183747450747 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183747450747 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481854358 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481854358 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218229305105 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218229305105 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030726 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030726 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.124526 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124526 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143793 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143793 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030312 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030312 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11106.835074 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11106.835074 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14557.475837 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14557.475837 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16020.645487 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16020.645487 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20929.339712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20929.339712 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2409,10 +2392,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1759208062571 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1759208062571 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1759755743315 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1759755743315 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 7c26dcd5b..74aa0b266 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,192 +1,174 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.607932 # Number of seconds simulated -sim_ticks 2607931908500 # Number of ticks simulated -final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.607938 # Number of seconds simulated +sim_ticks 2607938427000 # Number of ticks simulated +final_tick 2607938427000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43892 # Simulator instruction rate (inst/s) -host_op_rate 52863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1823841209 # Simulator tick rate (ticks/s) -host_mem_usage 431084 # Number of bytes of host memory used -host_seconds 1429.91 # Real time elapsed on the host -sim_insts 62761278 # Number of instructions simulated -sim_ops 75589768 # Number of ops (including micro ops) simulated +host_inst_rate 67776 # Simulator instruction rate (inst/s) +host_op_rate 81630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2816320200 # Simulator tick rate (ticks/s) +host_mem_usage 438748 # Number of bytes of host memory used +host_seconds 926.01 # Real time elapsed on the host +sim_insts 62761521 # Number of instructions simulated +sim_ops 75590331 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 121488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 457468 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 4606656 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory -system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 70992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 622136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5389248 # Number of bytes read from this memory +system.physmem.bytes_read::total 132379476 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 121488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 70992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 192480 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4393536 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory +system.physmem.bytes_written::total 7422672 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 4422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 7207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 71979 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1152 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 84207 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15317537 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 68649 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 825933 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46439182 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 98 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 46584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 175414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1766398 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 238555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 2066478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50760200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 46584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27222 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 73805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1684678 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1154987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2846184 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1684678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46439182 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1767285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 98 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 46584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 181932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1766398 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15317443 # Number of read requests accepted -system.physmem.writeReqs 825902 # Number of write requests accepted -system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue -system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 957415 # Per bank write bursts -system.physmem.perBankRdBursts::1 954356 # Per bank write bursts -system.physmem.perBankRdBursts::2 951532 # Per bank write bursts -system.physmem.perBankRdBursts::3 951095 # Per bank write bursts -system.physmem.perBankRdBursts::4 960453 # Per bank write bursts -system.physmem.perBankRdBursts::5 954333 # Per bank write bursts -system.physmem.perBankRdBursts::6 950562 # Per bank write bursts -system.physmem.perBankRdBursts::7 950350 # Per bank write bursts -system.physmem.perBankRdBursts::8 957423 # Per bank write bursts -system.physmem.perBankRdBursts::9 955252 # Per bank write bursts -system.physmem.perBankRdBursts::10 950399 # Per bank write bursts -system.physmem.perBankRdBursts::11 949996 # Per bank write bursts -system.physmem.perBankRdBursts::12 957025 # Per bank write bursts -system.physmem.perBankRdBursts::13 954231 # Per bank write bursts -system.physmem.perBankRdBursts::14 950565 # Per bank write bursts -system.physmem.perBankRdBursts::15 950154 # Per bank write bursts -system.physmem.perBankWrBursts::0 7537 # Per bank write bursts -system.physmem.perBankWrBursts::1 7271 # Per bank write bursts -system.physmem.perBankWrBursts::2 7519 # Per bank write bursts -system.physmem.perBankWrBursts::3 7339 # Per bank write bursts -system.physmem.perBankWrBursts::4 7525 # Per bank write bursts -system.physmem.perBankWrBursts::5 7506 # Per bank write bursts -system.physmem.perBankWrBursts::6 7304 # Per bank write bursts -system.physmem.perBankWrBursts::7 7173 # Per bank write bursts -system.physmem.perBankWrBursts::8 7520 # Per bank write bursts -system.physmem.perBankWrBursts::9 7613 # Per bank write bursts -system.physmem.perBankWrBursts::10 6934 # Per bank write bursts -system.physmem.perBankWrBursts::11 6533 # Per bank write bursts -system.physmem.perBankWrBursts::12 7225 # Per bank write bursts -system.physmem.perBankWrBursts::13 7011 # Per bank write bursts -system.physmem.perBankWrBursts::14 7249 # Per bank write bursts -system.physmem.perBankWrBursts::15 7053 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 27222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1393542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 2066478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53606384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15317537 # Number of read requests accepted +system.physmem.writeReqs 825933 # Number of write requests accepted +system.physmem.readBursts 15317537 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 825933 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976408384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3913984 # Total number of bytes read from write queue +system.physmem.bytesWritten 7445376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132379476 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7422672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 61156 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709570 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15921 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 957324 # Per bank write bursts +system.physmem.perBankRdBursts::1 954296 # Per bank write bursts +system.physmem.perBankRdBursts::2 951048 # Per bank write bursts +system.physmem.perBankRdBursts::3 951190 # Per bank write bursts +system.physmem.perBankRdBursts::4 960560 # Per bank write bursts +system.physmem.perBankRdBursts::5 954642 # Per bank write bursts +system.physmem.perBankRdBursts::6 950634 # Per bank write bursts +system.physmem.perBankRdBursts::7 950367 # Per bank write bursts +system.physmem.perBankRdBursts::8 957475 # Per bank write bursts +system.physmem.perBankRdBursts::9 955236 # Per bank write bursts +system.physmem.perBankRdBursts::10 950657 # Per bank write bursts +system.physmem.perBankRdBursts::11 950055 # Per bank write bursts +system.physmem.perBankRdBursts::12 957021 # Per bank write bursts +system.physmem.perBankRdBursts::13 954396 # Per bank write bursts +system.physmem.perBankRdBursts::14 950984 # Per bank write bursts +system.physmem.perBankRdBursts::15 950496 # Per bank write bursts +system.physmem.perBankWrBursts::0 7473 # Per bank write bursts +system.physmem.perBankWrBursts::1 7236 # Per bank write bursts +system.physmem.perBankWrBursts::2 7209 # Per bank write bursts +system.physmem.perBankWrBursts::3 7113 # Per bank write bursts +system.physmem.perBankWrBursts::4 7623 # Per bank write bursts +system.physmem.perBankWrBursts::5 7510 # Per bank write bursts +system.physmem.perBankWrBursts::6 7170 # Per bank write bursts +system.physmem.perBankWrBursts::7 7098 # Per bank write bursts +system.physmem.perBankWrBursts::8 7538 # Per bank write bursts +system.physmem.perBankWrBursts::9 7733 # Per bank write bursts +system.physmem.perBankWrBursts::10 7167 # Per bank write bursts +system.physmem.perBankWrBursts::11 6553 # Per bank write bursts +system.physmem.perBankWrBursts::12 7248 # Per bank write bursts +system.physmem.perBankWrBursts::13 7122 # Per bank write bursts +system.physmem.perBankWrBursts::14 7350 # Per bank write bursts +system.physmem.perBankWrBursts::15 7191 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2607930021000 # Total gap between requests +system.physmem.totGap 2607936588500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) system.physmem.readPktSize::3 15138841 # Read request sizes (log2) -system.physmem.readPktSize::4 3437 # Read request sizes (log2) +system.physmem.readPktSize::4 3422 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175106 # Read request sizes (log2) +system.physmem.readPktSize::6 175215 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68618 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1043990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2669652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2569034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3344990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 138441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 119851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 110072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 105368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68649 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1023042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1020695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 981592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1089381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 978756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1042832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2673243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2574268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3352848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 134504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 107699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19722 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -202,45 +184,45 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -251,57 +233,57 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1020745 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.858515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 884.982288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 219.503901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 33091 3.24% 3.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19420 1.90% 5.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8756 0.86% 6.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2666 0.26% 6.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3150 0.31% 6.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2102 0.21% 6.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8576 0.84% 7.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1045 0.10% 7.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941939 92.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1020745 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6738 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2264.229742 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98171.784681 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6732 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6738 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6738 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.265361 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.193186 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.647301 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3643 54.07% 54.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 48 0.71% 54.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1665 24.71% 79.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1002 14.87% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 147 2.18% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 65 0.96% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 57 0.85% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 53 0.79% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 33 0.49% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 11 0.16% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.13% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads -system.physmem.totQLat 400005056750 # Total ticks spent queuing -system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6738 # Writes before turning the bus around for reads +system.physmem.totQLat 399562219250 # Total ticks spent queuing +system.physmem.totMemAccLat 685619363000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76281905000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26189.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44939.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s @@ -309,546 +291,565 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.95 # Data bus utilization in percentage system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing -system.physmem.readRowHits 14262971 # Number of row buffer hits during reads -system.physmem.writeRowHits 87526 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.38 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.08 # Average write queue length when enqueuing +system.physmem.readRowHits 14264224 # Number of row buffer hits during reads +system.physmem.writeRowHits 87746 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes -system.physmem.avgGap 161548.30 # Average gap between requests +system.physmem.writeRowHitRate 75.41 # Row buffer hit rate for writes +system.physmem.avgGap 161547.46 # Average gap between requests system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states -system.physmem.memoryStateTime::REF 87084400000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2277806510000 # Time in different power states +system.physmem.memoryStateTime::REF 87084660000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states +system.physmem.memoryStateTime::ACT 243043451250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.trans_dist::ReadReq 16496763 # Transaction distribution -system.membus.trans_dist::ReadResp 16496763 # Transaction distribution -system.membus.trans_dist::WriteReq 769202 # Transaction distribution -system.membus.trans_dist::WriteResp 769202 # Transaction distribution -system.membus.trans_dist::Writeback 68618 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution -system.membus.trans_dist::ReadExReq 15703 # Transaction distribution -system.membus.trans_dist::ReadExResp 8933 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 16496833 # Transaction distribution +system.membus.trans_dist::ReadResp 16496833 # Transaction distribution +system.membus.trans_dist::WriteReq 769198 # Transaction distribution +system.membus.trans_dist::WriteResp 769198 # Transaction distribution +system.membus.trans_dist::Writeback 68649 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58344 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 23631 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15921 # Transaction distribution +system.membus.trans_dist::ReadExReq 15704 # Transaction distribution +system.membus.trans_dist::ReadExResp 8956 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384374 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13882 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045303 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4445635 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34723267 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392689 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27764 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21107657 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18691620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21116357 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 142218185 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 72850 # Total snoops (count) -system.membus.snoop_fanout::samples 332577 # Request fanout histogram +system.membus.pkt_size::total 142226885 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 72802 # Total snoops (count) +system.membus.snoop_fanout::samples 332587 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332577 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332587 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332577 # Request fanout histogram -system.membus.reqLayer0.occupancy 1569259492 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332587 # Request fanout histogram +system.membus.reqLayer0.occupancy 1569233990 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11956494 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11974494 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1552000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1549500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17698783999 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17698127000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5007965719 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5007859946 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37372928091 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37384021831 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 91666 # number of replacements -system.l2c.tags.tagsinuse 54831.199714 # Cycle average of tags in use -system.l2c.tags.total_refs 387443 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 156491 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.475817 # Average number of references to valid blocks. +system.l2c.tags.replacements 91703 # number of replacements +system.l2c.tags.tagsinuse 54901.298749 # Cycle average of tags in use +system.l2c.tags.total_refs 387577 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156499 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.476546 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 7736.589041 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.331203 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.025467 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 672.803532 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1677.780077 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24285.244228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.407687 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 678.722766 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3493.963497 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16278.332216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.118051 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 7788.394578 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.341349 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 2.981982 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 674.734753 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1668.636810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24293.005252 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.419961 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 676.905989 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3493.827255 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16296.050819 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.118841 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000020 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.010266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.025601 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370563 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.010296 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.025461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370682 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.053314 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248388 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.836658 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 52524 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 12291 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5897 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 46469 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2272 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 9679 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.801453 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.187546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5049935 # Number of tag accesses -system.l2c.tags.data_accesses 5049935 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 116 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 44 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 4746 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 14884 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72204 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 72 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7407 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 16636 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 74707 # number of ReadReq hits -system.l2c.ReadReq_hits::total 190984 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 213987 # number of Writeback hits -system.l2c.Writeback_hits::total 213987 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3107 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2045 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5152 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 90 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 245 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 1803 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2746 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4549 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 44 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 4746 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 16687 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 72204 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 72 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7407 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 19382 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 74707 # number of demand (read+write) hits -system.l2c.demand_hits::total 195533 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 44 # number of overall hits -system.l2c.overall_hits::cpu0.inst 4746 # number of overall hits -system.l2c.overall_hits::cpu0.data 16687 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 72204 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 168 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 72 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7407 # number of overall hits -system.l2c.overall_hits::cpu1.data 19382 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 74707 # number of overall hits -system.l2c.overall_hits::total 195533 # number of overall hits +system.l2c.tags.occ_percent::cpu1.inst 0.010329 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.053312 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248658 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.837727 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 52420 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 12367 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 215 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5971 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 46232 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2304 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 9709 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.799866 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.188705 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5051801 # Number of tag accesses +system.l2c.tags.data_accesses 5051801 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 125 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 40 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 4738 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 15024 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72119 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 182 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 64 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 7352 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 16354 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75111 # number of ReadReq hits +system.l2c.ReadReq_hits::total 191109 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 213952 # number of Writeback hits +system.l2c.Writeback_hits::total 213952 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3082 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2112 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 5194 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 89 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 239 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 1876 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2742 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4618 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 125 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 40 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 4738 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 16900 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 72119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 182 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 64 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7352 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 19096 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 75111 # number of demand (read+write) hits +system.l2c.demand_hits::total 195727 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 125 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 40 # number of overall hits +system.l2c.overall_hits::cpu0.inst 4738 # number of overall hits +system.l2c.overall_hits::cpu0.data 16900 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 72119 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 182 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 64 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7352 # number of overall hits +system.l2c.overall_hits::cpu1.data 19096 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 75111 # number of overall hits +system.l2c.overall_hits::total 195727 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 1063 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 3259 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 1057 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 3257 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 71979 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1104 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4621 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq misses -system.l2c.ReadReq_misses::total 166173 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 7830 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5610 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13440 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1272 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1187 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2459 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 3945 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5092 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 9037 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 1095 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4649 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84207 # number of ReadReq misses +system.l2c.ReadReq_misses::total 166259 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 7810 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5551 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13361 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1270 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1186 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2456 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 3938 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5122 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 9060 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 1063 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 7204 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 1057 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 7195 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 71979 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1104 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9713 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) misses -system.l2c.demand_misses::total 175210 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1095 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9771 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 84207 # number of demand (read+write) misses +system.l2c.demand_misses::total 175319 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 1063 # number of overall misses -system.l2c.overall_misses::cpu0.data 7204 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 72015 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 1057 # number of overall misses +system.l2c.overall_misses::cpu0.data 7195 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 71979 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1104 # number of overall misses -system.l2c.overall_misses::cpu1.data 9713 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 84097 # number of overall misses -system.l2c.overall_misses::total 175210 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 88517249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 251848999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 744500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 96486500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 359268498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17143743646 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 12214974 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 6369731 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 18584705 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 508980 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4358314 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4867294 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 294129193 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 380271953 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 674401146 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 195250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 88517249 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 545978192 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 744500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 96486500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 739540451 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17818144792 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 195250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 182000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 88517249 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 545978192 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 744500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 96486500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 739540451 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17818144792 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 119 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 47 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 5809 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 18143 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144219 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 176 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 72 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 8511 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 21257 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 158804 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 357157 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 213987 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 213987 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10937 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 7655 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18592 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1362 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1432 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2794 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 5748 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 7838 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 13586 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 119 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 47 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 5809 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 23891 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144219 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 176 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 72 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8511 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 29095 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 158804 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 370743 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 119 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 47 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 5809 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 23891 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144219 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 176 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 72 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 8511 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 29095 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 158804 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 370743 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.063830 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.182992 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.179629 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.129714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.217387 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.465266 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.715918 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.732854 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.722892 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.933921 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.828911 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.880100 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.686326 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.649656 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.665170 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.063830 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.182992 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.301536 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.129714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.333837 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.472592 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.063830 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.182992 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.301536 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.129714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.333837 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.472592 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83271.165569 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 77277.999079 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87397.192029 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77746.915819 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 103168.045627 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1560.022222 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1135.424421 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1382.790551 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 400.141509 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3671.705139 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1979.379423 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74557.463371 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74680.273566 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 74626.662167 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 101695.935118 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 101695.935118 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 369 # number of cycles access was blocked +system.l2c.overall_misses::cpu1.inst 1095 # number of overall misses +system.l2c.overall_misses::cpu1.data 9771 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 84207 # number of overall misses +system.l2c.overall_misses::total 175319 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 219750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 271250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 87748250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 250538998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 662750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 96997750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 362821248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17132951668 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11966992 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 6050751 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 18017743 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 511478 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4288817 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4800295 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 296071197 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 384274697 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 680345894 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 219750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 271250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 87748250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 546610195 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 662750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 96997750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 747095945 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17813297562 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 219750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 271250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 87748250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 546610195 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 662750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 96997750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 747095945 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17813297562 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 128 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 44 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 5795 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 18281 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144098 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 190 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 64 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 8447 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 21003 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 159318 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 357368 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 213952 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 213952 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10892 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 7663 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18555 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1359 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1425 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2784 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 5814 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 7864 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 13678 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 128 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 44 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 5795 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 24095 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144098 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 190 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 64 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8447 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 28867 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 159318 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 371046 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 128 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 44 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 5795 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 24095 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144098 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 190 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 64 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8447 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 28867 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 159318 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 371046 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.090909 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.182399 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.178163 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.129632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.221349 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.465232 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.717040 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.724390 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.720075 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934511 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.832281 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.882184 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.677331 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.651322 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.662378 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.090909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.182399 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.298610 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.129632 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.338483 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.472499 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.090909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.182399 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.298610 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.129632 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.338483 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.472499 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 73250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 67812.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83016.319773 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 76923.241633 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95569.869406 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82843.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88582.420091 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78042.858249 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112278.884677 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 103049.769745 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1532.265301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1090.029004 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1348.532520 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 402.738583 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3616.203204 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1954.517508 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 75183.137887 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75024.345373 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 75093.365784 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 73250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 67812.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 83016.319773 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 75970.840167 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95569.869406 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82843.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 88582.420091 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76460.540886 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112278.884677 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 101605.060273 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 73250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 67812.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 83016.319773 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 75970.840167 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95569.869406 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82843.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 88582.420091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76460.540886 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112278.884677 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 101605.060273 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 36.900000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 68618 # number of writebacks -system.l2c.writebacks::total 68618 # number of writebacks +system.l2c.writebacks::writebacks 68649 # number of writebacks +system.l2c.writebacks::total 68649 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 1063 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 3259 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 1057 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 3257 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 71979 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1104 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4621 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 166173 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 7830 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5610 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 13440 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1272 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1187 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2459 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 3945 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5092 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 9037 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1095 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4649 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 84207 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 166259 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 7810 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5551 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 13361 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1270 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1186 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2456 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 3938 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5122 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 9060 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 1063 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 7204 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 1057 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 7195 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 71979 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1104 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9713 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 175210 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1095 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9771 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 84207 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 175319 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 1063 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 7204 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 1057 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 7195 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 71979 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1104 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9713 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 175210 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 145000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 75361749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 211101499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 645000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 82874000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 301675998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15091446656 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 79003615 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56662566 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 135666181 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12832754 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11966179 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 24798933 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 244772807 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 316260047 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 561032854 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 75361749 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 455874306 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 645000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 82874000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 617936045 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15652479510 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 75361749 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 455874306 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 645000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 82874000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 617936045 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15652479510 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 178129250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343853503 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3278250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154953535743 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167478796746 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076363997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16025248776 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17101612773 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 178129250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420217500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3278250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978784519 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184580409519 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179629 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217387 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.465266 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.715918 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.732854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.722892 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.933921 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828911 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.880100 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.686326 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.649656 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.665170 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.472592 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.472592 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64774.930654 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65283.704393 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 90817.681910 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.861430 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10100.279144 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10094.209896 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 1095 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9771 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 84207 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 175319 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 182750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 221250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 74667250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 209834998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 5986714130 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 563750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 83479750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 304868248 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 8418931550 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15079463676 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 78934077 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56101003 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 135035080 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12761264 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11939675 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 24700939 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 246811801 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 319899303 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 566711104 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 182750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 221250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 74667250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 456646799 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5986714130 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 563750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 83479750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 624767551 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8418931550 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 15646174780 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 182750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 221250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 74667250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 456646799 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5986714130 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 563750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 83479750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 624767551 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8418931550 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 15646174780 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 177326500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343963753 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3540500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154954228993 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167479059746 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076373001 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16024726896 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17101099897 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 177326500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420336754 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3540500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978955889 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184580159643 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.178163 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.221349 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.465232 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.717040 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.724390 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.720075 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934511 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.832281 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.882184 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.677331 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.651322 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.662378 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.298610 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.338483 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.472499 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.298610 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.338483 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.472499 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64425.851397 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65577.166703 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 90698.630907 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10106.796031 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.467844 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10106.659681 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10048.239370 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10067.179595 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10057.385586 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62674.403504 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62455.935767 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62550.894481 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63467.241001 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63941.004094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 89244.033904 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63467.241001 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63941.004094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 89244.033904 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -869,48 +870,48 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 177868 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1651156 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1651155 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769198 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769198 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 213952 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 63434 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 23959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 87393 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 23242 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 23242 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760832 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337498 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5098330 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18164043 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24784826 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 42948869 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 177697 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 784039 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 784039 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 784039 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2614289788 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1150553389 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2660791344 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution +system.iobus.trans_dist::ReadReq 16322919 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322919 # Transaction distribution system.iobus.trans_dist::WriteReq 8084 # Transaction distribution system.iobus.trans_dist::WriteResp 8084 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8838 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -932,12 +933,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384374 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32662006 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17676 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -959,13 +960,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392689 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123503217 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4425000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1011,19 +1012,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376290000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38179589169 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6445077 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits +system.cpu0.branchPred.lookups 6443222 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4514499 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 302125 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3729781 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2837348 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.072777 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 778118 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 15176 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1047,25 +1048,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6738270 # DTB read hits -system.cpu0.dtb.read_misses 20792 # DTB read misses -system.cpu0.dtb.write_hits 5108254 # DTB write hits -system.cpu0.dtb.write_misses 4938 # DTB write misses +system.cpu0.dtb.read_hits 6735842 # DTB read hits +system.cpu0.dtb.read_misses 20815 # DTB read misses +system.cpu0.dtb.write_hits 5107742 # DTB write hits +system.cpu0.dtb.write_misses 5078 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 367 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6759062 # DTB read accesses -system.cpu0.dtb.write_accesses 5113192 # DTB write accesses +system.cpu0.dtb.read_accesses 6756657 # DTB read accesses +system.cpu0.dtb.write_accesses 5112820 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11846524 # DTB hits -system.cpu0.dtb.misses 25730 # DTB misses -system.cpu0.dtb.accesses 11872254 # DTB accesses +system.cpu0.dtb.hits 11843584 # DTB hits +system.cpu0.dtb.misses 25893 # DTB misses +system.cpu0.dtb.accesses 11869477 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1087,8 +1088,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 11251934 # ITB inst hits -system.cpu0.itb.inst_misses 5844 # ITB inst misses +system.cpu0.itb.inst_hits 11247992 # ITB inst hits +system.cpu0.itb.inst_misses 5846 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1097,143 +1098,143 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1213 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2388 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses -system.cpu0.itb.hits 11251934 # DTB hits -system.cpu0.itb.misses 5844 # DTB misses -system.cpu0.itb.accesses 11257778 # DTB accesses -system.cpu0.numCycles 70547986 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 11253838 # ITB inst accesses +system.cpu0.itb.hits 11247992 # DTB hits +system.cpu0.itb.misses 5846 # DTB misses +system.cpu0.itb.accesses 11253838 # DTB accesses +system.cpu0.numCycles 70572029 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 4765934 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 34354024 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6443222 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3615466 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61748976 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 827418 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 76155 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 31280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 103338 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 2296149 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 8939 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 11248771 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 69018 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1645 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 69444480 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.597050 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.081482 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 50353589 72.51% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 6606705 9.51% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2597434 3.74% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 9886752 14.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 69444480 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.091300 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.486794 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 6420501 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48533578 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12241748 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1929473 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 319180 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 871648 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 96104 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 34913571 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 1200749 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 319180 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 8404067 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 22318095 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 11023940 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 12127048 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 15252150 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 33557627 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 347095 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 4724247 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2950612 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 10590884 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 2755476 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 34851569 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 154470161 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 39932563 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3839 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30129647 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4721913 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 454205 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 374005 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4735093 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6116299 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5560853 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 585692 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 726458 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 32313533 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 795864 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 32787954 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 169648 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 3622039 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 7620869 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 145783 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 69444480 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.472146 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.871579 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50308599 72.44% 72.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9186806 13.23% 85.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 6613722 9.52% 95.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2968134 4.27% 99.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 366793 0.53% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 426 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 69444480 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2914015 33.72% 33.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 370 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 2945355 34.08% 67.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 2781781 32.19% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14545 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 20237485 61.72% 61.77% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42714 0.13% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued @@ -1257,101 +1258,101 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7055748 21.52% 83.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5436782 16.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued -system.cpu0.iq.rate 0.464855 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 32787954 # Type of FU issued +system.cpu0.iq.rate 0.464603 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8641521 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.263558 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 143819965 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 36733067 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 31072945 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11591 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 41407644 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7286 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 165926 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 774444 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 6361 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 333599 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1087774 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 167955 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 319180 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7637637 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6671195 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 33211836 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 6116299 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5560853 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 485055 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 10847 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6650997 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 6361 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 101358 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 128388 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 229746 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 32419905 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 6900946 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 342549 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 102446 # number of nop insts executed -system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4700114 # Number of branches executed -system.cpu0.iew.exec_stores 5379801 # Number of stores executed -system.cpu0.iew.exec_rate 0.459648 # Inst execution rate -system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 15739944 # num instructions producing a value -system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value +system.cpu0.iew.exec_nop 102439 # number of nop insts executed +system.cpu0.iew.exec_refs 12280176 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4698919 # Number of branches executed +system.cpu0.iew.exec_stores 5379230 # Number of stores executed +system.cpu0.iew.exec_rate 0.459387 # Inst execution rate +system.cpu0.iew.wb_sent 32226620 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 31076783 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 15728135 # num instructions producing a value +system.cpu0.iew.wb_consumers 27168028 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.440356 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.578921 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 3251168 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 650081 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 207596 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 68809072 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.427174 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.181510 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54941660 79.85% 79.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7926001 11.52% 91.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2553754 3.71% 95.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1118993 1.63% 96.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 777653 1.13% 97.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 424728 0.62% 98.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 260082 0.38% 98.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 241415 0.35% 99.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 564786 0.82% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24068410 # Number of instructions committed -system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 68809072 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24063345 # Number of instructions committed +system.cpu0.commit.committedOps 29393425 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10570507 # Number of memory references committed -system.cpu0.commit.loads 5342633 # Number of loads committed -system.cpu0.commit.membars 231974 # Number of memory barriers committed -system.cpu0.commit.branches 4351471 # Number of branches committed +system.cpu0.commit.refs 10569108 # Number of memory references committed +system.cpu0.commit.loads 5341854 # Number of loads committed +system.cpu0.commit.membars 231843 # Number of memory barriers committed +system.cpu0.commit.branches 4350514 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499778 # Number of function calls committed. +system.cpu0.commit.int_insts 25739481 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499600 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 18783880 63.91% 63.91% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39757 0.14% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction @@ -1375,523 +1376,523 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 5341854 18.17% 82.22% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5227254 17.78% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction -system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 29393425 # Class of committed instruction +system.cpu0.commit.bw_lim_events 564786 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 99997744 # The number of ROB reads -system.cpu0.rob.rob_writes 65895627 # The number of ROB writes -system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23987668 # Number of Instructions Simulated -system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads -system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads +system.cpu0.rob.rob_reads 100015321 # The number of ROB reads +system.cpu0.rob.rob_writes 65887471 # The number of ROB writes +system.cpu0.timesIdled 89304 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1127549 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5145313600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23982603 # Number of Instructions Simulated +system.cpu0.committedOps 29312683 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.942634 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.942634 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.339832 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.339832 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 37149809 # number of integer regfile reads +system.cpu0.int_regfile_writes 18849024 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads system.cpu0.fp_regfile_writes 840 # number of floating regfile writes -system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads -system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes -system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads -system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes -system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 640729 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram +system.cpu0.cc_regfile_reads 113743711 # number of cc regfile reads +system.cpu0.cc_regfile_writes 12811786 # number of cc regfile writes +system.cpu0.misc_regfile_reads 112044501 # number of misc regfile reads +system.cpu0.misc_regfile_writes 501943 # number of misc regfile writes +system.cpu0.toL2Bus.trans_dist::ReadReq 900890 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 693810 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 10816 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 10816 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 228377 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 268020 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 56323 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24618 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 62769 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 133666 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 124628 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651345 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1224806 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16460 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46873 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 1939484 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20679616 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38657675 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27344 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 81552 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 59446187 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 639427 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 1524092 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.371625 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.483239 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 957702 62.84% 62.84% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 566390 37.16% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 1524092 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 762289909 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 71201999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 71149999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 488209636 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 613319434 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 613845688 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 9639487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 9628741 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 26428702 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 26509702 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 322116 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 321808 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.716294 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10911549 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 322320 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.853155 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6537059000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.716294 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999446 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999446 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 22821148 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 22821148 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 10915164 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10915164 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 10915164 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10915164 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 10915164 # number of overall hits -system.cpu0.icache.overall_hits::total 10915164 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 334091 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 334091 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 334091 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 334091 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 334091 # number of overall misses -system.cpu0.icache.overall_misses::total 334091 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863305358 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 2863305358 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 2863305358 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 2863305358 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 2863305358 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 2863305358 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 11249255 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11249255 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 11249255 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11249255 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 11249255 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11249255 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029699 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029699 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029699 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029699 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029699 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029699 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8570.435474 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8570.435474 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8570.435474 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8570.435474 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 177531 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 22346 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 22813002 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 22813002 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 10911549 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10911549 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 10911549 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10911549 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 10911549 # number of overall hits +system.cpu0.icache.overall_hits::total 10911549 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 333786 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 333786 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 333786 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 333786 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 333786 # number of overall misses +system.cpu0.icache.overall_misses::total 333786 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863204339 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 2863204339 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 2863204339 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 2863204339 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 2863204339 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 2863204339 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 11245335 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11245335 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 11245335 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11245335 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 11245335 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11245335 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029682 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029682 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029682 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029682 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029682 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029682 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8577.964142 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8577.964142 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8577.964142 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8577.964142 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8577.964142 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8577.964142 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 178990 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 306 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 22304 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.944643 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 61.400000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8.025018 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 61.200000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11453 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 11453 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 11453 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 11453 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 11453 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 11453 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322638 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 322638 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 322638 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 322638 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 322638 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 322638 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310628588 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310628588 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310628588 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 2310628588 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310628588 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 2310628588 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 272886999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 272886999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 272886999 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 272886999 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028681 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028681 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028681 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7161.675277 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11454 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 11454 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 11454 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 11454 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 11454 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 11454 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322332 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 322332 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 322332 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 322332 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 322332 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 322332 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310843125 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310843125 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310843125 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 2310843125 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310843125 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 2310843125 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 271667749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 271667749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 271667749 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 271667749 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028664 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028664 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028664 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7169.139660 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7169.139660 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7169.139660 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529222 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247992 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2979692 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86609 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529022 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247159 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2982180 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86515 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16169 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 196999 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 262402 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 165160 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15951.411231 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 747099 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 181321 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.120311 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 4999805500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4772.372752 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.637155 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.084033 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 735.053900 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1518.442449 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.291283 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000710 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000066 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044864 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092678 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543995 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.973597 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7338 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8811 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1027 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5229 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 943 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 165246 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15954.893231 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 747835 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 181374 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.123165 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 4999584000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4776.473696 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.474561 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.133588 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 734.105729 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1523.434218 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8907.271439 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.291533 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000761 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000069 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044806 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092983 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543657 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.973809 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7357 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8758 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 33 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 96 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1021 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5218 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 989 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1656 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6017 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.447876 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.537781 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 15517001 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 15517001 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 19658 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6554 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314769 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 162769 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 503750 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 228045 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 228045 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6593 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 6593 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 622 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 622 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95529 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 95529 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 19658 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6554 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 314769 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 258298 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 599279 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 19658 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6554 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 314769 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 258298 # number of overall hits -system.cpu0.l2cache.overall_hits::total 599279 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 345 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7801 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 50805 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 59122 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19680 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 19680 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10856 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 10856 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23597 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 23597 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 345 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 7801 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 74402 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 82719 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 345 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 7801 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 74402 # number of overall misses -system.cpu0.l2cache.overall_misses::total 82719 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7498249 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3753000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 255179729 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1303745054 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1570176032 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 310997961 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 310997961 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 212766148 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 212766148 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 609000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 609000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 893661798 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 893661798 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7498249 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3753000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 255179729 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 2197406852 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 2463837830 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7498249 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3753000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 255179729 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 2197406852 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 2463837830 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20003 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6725 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322570 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213574 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 562872 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 228050 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 228050 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11478 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 11478 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119126 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 119126 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20003 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6725 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 322570 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 332700 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 681998 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20003 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6725 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 322570 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 332700 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 681998 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025428 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024184 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.237880 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.105036 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000022 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000022 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.749058 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.749058 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.945809 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.945809 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 470 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1658 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5972 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 621 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.449036 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.534546 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 15532089 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 15532089 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 20030 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6663 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314349 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 163060 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 504102 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 228376 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 228376 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6687 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 6687 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 642 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 642 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95716 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 95716 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 20030 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6663 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 314349 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 258776 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 599818 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 20030 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6663 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 314349 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 258776 # number of overall hits +system.cpu0.l2cache.overall_hits::total 599818 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 358 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7928 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 50645 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 59104 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19619 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 19619 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10843 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 10843 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23636 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 23636 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 358 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 7928 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 74281 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 82740 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 358 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 7928 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 74281 # number of overall misses +system.cpu0.l2cache.overall_misses::total 82740 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7810749 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3821249 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 257932474 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1300025301 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1569589773 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 308952932 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 308952932 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 211975648 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 211975648 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 651000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 651000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 895614551 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 895614551 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7810749 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3821249 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 257932474 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 2195639852 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 2465204324 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7810749 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3821249 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 257932474 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 2195639852 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 2465204324 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20388 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6836 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322277 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213705 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 563206 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 228377 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 228377 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26306 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26306 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11485 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 11485 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119352 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 119352 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20388 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6836 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 322277 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 333057 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 682558 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20388 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6836 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 322277 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 333057 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 682558 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025307 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024600 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.236986 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.104942 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745799 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745799 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.944101 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.944101 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198084 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198084 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025428 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024184 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223631 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.121289 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025428 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024184 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223631 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.121289 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21947.368421 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32711.156134 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25661.746954 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26558.236054 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15802.741921 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15802.741921 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19598.945099 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19598.945099 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 609000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 609000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37871.839556 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37871.839556 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 29785.633651 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 29785.633651 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 4781 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198036 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198036 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025307 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024600 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223028 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.121220 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025307 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024600 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223028 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.121220 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22088.144509 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32534.368567 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25669.371132 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26556.405201 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15747.639125 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15747.639125 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19549.538689 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19549.538689 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 325500 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 325500 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37891.967803 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37891.967803 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22088.144509 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32534.368567 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29558.566147 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 29794.589364 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22088.144509 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32534.368567 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29558.566147 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 29794.589364 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 7107 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 266 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 273 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 17.973684 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 26.032967 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 105131 # number of writebacks -system.cpu0.l2cache.writebacks::total 105131 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 105341 # number of writebacks +system.cpu0.l2cache.writebacks::total 105341 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1845 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 997 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 936 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 936 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1954 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 952 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 2908 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 913 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 913 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1845 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1933 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3780 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1954 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1865 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3821 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1845 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1933 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3780 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 344 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 170 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5956 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49808 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 56278 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 198779 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19680 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19680 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10856 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10856 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22661 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 22661 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 344 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 170 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5956 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72469 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 78939 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 344 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 170 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5956 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72469 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 277718 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2550500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 181100759 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 940424592 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1129080602 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8151036272 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 354005766 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 354005766 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158485722 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158485722 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 490000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 490000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 601346170 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 601346170 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2550500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 181100759 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541770762 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 1730426772 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2550500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 181100759 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541770762 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 9881463044 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244240750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865359008 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262027985 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 244240750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127386993 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15371627743 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.233212 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1954 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1865 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3821 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 357 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 172 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5974 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49693 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 56196 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 196993 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 196993 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19619 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19619 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10843 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10843 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22723 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 22723 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 357 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 172 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5974 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72416 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 78919 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 357 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 172 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5974 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72416 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 196993 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 275912 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2604249 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 180571011 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 937505841 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1125907352 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8176644028 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8176644028 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 352932260 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 352932260 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158150720 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158150720 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 518000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 518000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 604135928 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 604135928 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2604249 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 180571011 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541641769 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 1730043280 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2604249 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 180571011 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541641769 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8176644028 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 9906687308 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243146000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865472761 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14108618761 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262025986 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262025986 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 243146000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127498747 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15370644747 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.232531 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099779 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.945809 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745799 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745799 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.944101 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.944101 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190227 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190227 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115747 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190386 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190386 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217428 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115622 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217428 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.407212 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18880.994860 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20062.557340 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 490000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26536.612241 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26536.612241 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.062745 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35580.923973 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.404232 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18865.953776 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20035.364652 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41507.282127 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41507.282127 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17989.309343 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17989.309343 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14585.513234 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14585.513234 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 259000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 259000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26586.979184 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26586.979184 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21288.689917 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.758765 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21288.689917 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41507.282127 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35905.242643 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1901,192 +1902,192 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 297335 # number of replacements -system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 297776 # number of replacements +system.cpu0.dcache.tags.tagsinuse 472.735885 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9026842 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 298288 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.262169 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.916132 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 472.735885 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.923312 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.923312 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133505 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8636365 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8636365 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8681605 # number of overall hits -system.cpu0.dcache.overall_hits::total 8681605 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 322447 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 906986 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10798 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1304460 # number of overall misses -system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3662752641 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273467244 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 273467244 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 660000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 16742760911 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5058618 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5058618 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4807180 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4807180 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120267 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146149 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144984 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9865798 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9986065 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063742 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 20884973 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 20884973 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4735429 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4735429 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3898152 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3898152 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45417 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 45417 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135242 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 135242 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133435 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 133435 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8633581 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8633581 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8678998 # number of overall hits +system.cpu0.dcache.overall_hits::total 8678998 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 322548 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 322548 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 908505 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 908505 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 74956 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 74956 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10777 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10777 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11487 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 11487 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1231053 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1231053 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1306009 # number of overall misses +system.cpu0.dcache.overall_misses::total 1306009 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3690700649 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3690700649 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13101093488 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 13101093488 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182297251 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 182297251 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273170236 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 273170236 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 708000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 708000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 16791794137 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16791794137 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 16791794137 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16791794137 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5057977 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5057977 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4806657 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4806657 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120373 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 120373 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146019 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 146019 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144922 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144922 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9864634 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9864634 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9985007 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9985007 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063770 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063770 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.189010 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.189010 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.622698 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.622698 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073805 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073805 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079263 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079263 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124795 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.124795 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130797 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.130797 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11442.329976 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11442.329976 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14420.496847 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14420.496847 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16915.398627 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16915.398627 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23780.816227 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23780.816227 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13640.187821 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13640.187821 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12857.334166 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12857.334166 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 95 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1898059 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 100067 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.916667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18.967882 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks -system.cpu0.dcache.writebacks::total 228050 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44124 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 44124 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9611 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9611 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11479 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11479 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 304168 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 304168 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 348292 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 228377 # number of writebacks +system.cpu0.dcache.writebacks::total 228377 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162400 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 162400 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 764106 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 764106 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1174 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1174 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 926506 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 926506 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 926506 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 926506 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160148 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 160148 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144399 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 144399 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44137 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 44137 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9603 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9603 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 304547 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 304547 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 348684 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 348684 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1658754828 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1658754828 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2155336775 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2155336775 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 705733496 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 705733496 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 146716749 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146716749 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 248972764 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 248972764 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 670000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 670000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3814091603 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 3814091603 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4519825099 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4519825099 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541509738 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541509738 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345509995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345509995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15887019733 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15887019733 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031662 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031662 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030041 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030041 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366669 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366669 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065765 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065765 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079263 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079263 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030873 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030873 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034921 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034921 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10357.636861 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10357.636861 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14926.258319 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14926.258319 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15989.611800 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15989.611800 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15278.220244 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15278.220244 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21674.306956 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21674.306956 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12523.819322 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12523.819322 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12962.525091 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12962.525091 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -2094,15 +2095,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9149866 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits +system.cpu1.branchPred.lookups 9152424 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6787583 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 422463 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5824908 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4287107 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.599566 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 928023 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 19411 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2126,25 +2127,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25102636 # DTB read hits -system.cpu1.dtb.read_misses 30137 # DTB read misses -system.cpu1.dtb.write_hits 6841685 # DTB write hits -system.cpu1.dtb.write_misses 6769 # DTB write misses +system.cpu1.dtb.read_hits 25102485 # DTB read hits +system.cpu1.dtb.read_misses 30131 # DTB read misses +system.cpu1.dtb.write_hits 6842228 # DTB write hits +system.cpu1.dtb.write_misses 6831 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1185 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 216 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25132773 # DTB read accesses -system.cpu1.dtb.write_accesses 6848454 # DTB write accesses +system.cpu1.dtb.perms_faults 721 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25132616 # DTB read accesses +system.cpu1.dtb.write_accesses 6849059 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31944321 # DTB hits -system.cpu1.dtb.misses 36906 # DTB misses -system.cpu1.dtb.accesses 31981227 # DTB accesses +system.cpu1.dtb.hits 31944713 # DTB hits +system.cpu1.dtb.misses 36962 # DTB misses +system.cpu1.dtb.accesses 31981675 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2166,8 +2167,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 16803682 # ITB inst hits -system.cpu1.itb.inst_misses 6173 # ITB inst misses +system.cpu1.itb.inst_hits 16807994 # ITB inst hits +system.cpu1.itb.inst_misses 6151 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -2176,108 +2177,108 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1324 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2317 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses -system.cpu1.itb.hits 16803682 # DTB hits -system.cpu1.itb.misses 6173 # DTB misses -system.cpu1.itb.accesses 16809855 # DTB accesses -system.cpu1.numCycles 436917069 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16814145 # ITB inst accesses +system.cpu1.itb.hits 16807994 # DTB hits +system.cpu1.itb.misses 6151 # DTB misses +system.cpu1.itb.accesses 16814145 # DTB accesses +system.cpu1.numCycles 436928341 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7782698 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 51596763 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9152424 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5215130 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 424941710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 1120750 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 78139 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 42302 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 114025 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2394073 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 15193 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 16805493 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 110231 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1848 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 435928515 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.141220 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 0.582447 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 407583971 93.50% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 9418988 2.16% 95.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4633784 1.06% 96.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 14291772 3.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 435928515 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.020947 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.118090 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 9900364 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 404223223 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 17614980 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3776395 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 413553 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1053442 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 149008 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53092008 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1695759 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 413553 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13042723 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 210396712 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 23472613 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 17904868 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 170698046 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51368721 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 446510 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 60461955 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 44486739 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 161543607 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 5691516 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54461405 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 239791189 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 64663371 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6318 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 48773612 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 5687793 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 755066 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 650305 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9515083 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9672416 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7398818 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 540509 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 901013 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 49760651 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1064041 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 65151517 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 226257 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 4310331 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 9274124 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 164398 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 435928515 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.149455 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.502708 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 391744994 89.86% 89.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 28933513 6.64% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 10221564 2.34% 98.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4339119 1.00% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 689106 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 219 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 435928515 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4423159 17.50% 17.50% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available @@ -2306,130 +2307,130 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 17781771 70.36% 87.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3065221 12.13% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14259 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32355462 49.66% 49.68% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 60215 0.09% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 25491374 39.13% 88.91% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7228505 11.09% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued -system.cpu1.iq.rate 0.149104 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 65151517 # Type of FU issued +system.cpu1.iq.rate 0.149113 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 25270842 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.387878 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 591706993 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 55136909 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 48344835 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 21655 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8050 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6779 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 90394215 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 13885 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 164856 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 923073 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 694 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9989 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 405691 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16016634 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 154537 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 413553 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 90101438 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 101307050 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 50914326 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 9672416 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7398818 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 775912 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 15376 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 101229610 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9989 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 133261 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 167875 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301136 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 64660152 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25297767 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 454579 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 89541 # number of nop insts executed -system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6846575 # Number of branches executed -system.cpu1.iew.exec_stores 7146063 # Number of stores executed -system.cpu1.iew.exec_rate 0.147981 # Inst execution rate -system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25811466 # num instructions producing a value -system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value +system.cpu1.iew.exec_nop 89634 # number of nop insts executed +system.cpu1.iew.exec_refs 32444465 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6847399 # Number of branches executed +system.cpu1.iew.exec_stores 7146698 # Number of stores executed +system.cpu1.iew.exec_rate 0.147988 # Inst execution rate +system.cpu1.iew.wb_sent 64445126 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 48351614 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25812211 # num instructions producing a value +system.cpu1.iew.wb_consumers 39463324 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.110663 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.654081 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3859606 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899643 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 275641 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 435147565 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.106509 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.626853 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 413414233 95.01% 95.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12938839 2.97% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 3517188 0.81% 98.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1361627 0.31% 99.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1314784 0.30% 99.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 785099 0.18% 99.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 557735 0.13% 99.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 306330 0.07% 99.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 951730 0.22% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38843249 # Number of instructions committed -system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 435147565 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38848557 # Number of instructions committed +system.cpu1.commit.committedOps 46347287 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 15740654 # Number of memory references committed -system.cpu1.commit.loads 8748353 # Number of loads committed -system.cpu1.commit.membars 195273 # Number of memory barriers committed -system.cpu1.commit.branches 6419002 # Number of branches committed +system.cpu1.commit.refs 15742470 # Number of memory references committed +system.cpu1.commit.loads 8749343 # Number of loads committed +system.cpu1.commit.membars 195410 # Number of memory barriers committed +system.cpu1.commit.branches 6420016 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553431 # Number of function calls committed. +system.cpu1.commit.int_insts 41063846 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553629 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 30544997 65.90% 65.90% # Class of committed instruction system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction @@ -2458,511 +2459,499 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 8749343 18.88% 84.91% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6993127 15.09% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction -system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 46347287 # Class of committed instruction +system.cpu1.commit.bw_lim_events 951730 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 483317632 # The number of ROB reads -system.cpu1.rob.rob_writes 101136219 # The number of ROB writes -system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38773610 # Number of Instructions Simulated -system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads -system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads +system.cpu1.rob.rob_reads 483333475 # The number of ROB reads +system.cpu1.rob.rob_writes 101149089 # The number of ROB writes +system.cpu1.timesIdled 117660 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 999826 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4778389305 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38778918 # Number of Instructions Simulated +system.cpu1.committedOps 46277648 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 11.267162 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 11.267162 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.088753 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.088753 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 76052012 # number of integer regfile reads +system.cpu1.int_regfile_writes 30999334 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5023 # number of floating regfile reads system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes -system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads -system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes -system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads -system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes -system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution +system.cpu1.cc_regfile_reads 220747200 # number of cc regfile reads +system.cpu1.cc_regfile_writes 19380007 # number of cc regfile writes +system.cpu1.misc_regfile_reads 519889697 # number of misc regfile reads +system.cpu1.misc_regfile_writes 723831 # number of misc regfile writes +system.cpu1.toL2Bus.trans_dist::ReadReq 2172389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1977860 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 758382 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 758382 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 290106 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 274324 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 56101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25225 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 54306 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 595717 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 157043 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 149501 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1094031 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4942031 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17483 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65557 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 6119102 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34999952 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51368490 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29544 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86517802 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 597240 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1872325 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.291637 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.454516 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1326285 70.84% 70.84% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 546040 29.16% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1872325 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2993294877 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 46728999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 821422427 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 2122306221 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 10104485 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 36085284 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.icache.tags.replacements 546235 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 546512 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.931613 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16242826 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 547024 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.693077 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73724433000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.931613 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974476 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974476 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits -system.cpu1.icache.overall_hits::total 16238797 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses -system.cpu1.icache.overall_misses::total 562244 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 34157735 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34157735 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16242826 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16242826 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16242826 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16242826 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16242826 # number of overall hits +system.cpu1.icache.overall_hits::total 16242826 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 562520 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 562520 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 562520 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 562520 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 562520 # number of overall misses +system.cpu1.icache.overall_misses::total 562520 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4745618430 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4745618430 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4745618430 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4745618430 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4745618430 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4745618430 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16805346 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16805346 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16805346 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16805346 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16805346 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16805346 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033473 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033473 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033473 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033473 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033473 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033473 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.355027 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.355027 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.355027 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8436.355027 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.355027 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8436.355027 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 306365 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 40679 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.531281 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 1 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 546770 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 546770 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 546770 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15477 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 15477 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 15477 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 15477 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 15477 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 15477 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 547043 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 547043 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 547043 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 547043 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 547043 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 547043 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3841218666 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3841218666 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3841218666 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3841218666 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3841218666 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3841218666 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5375499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5375499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5375499 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5375499 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032552 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.032552 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.032552 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7021.785611 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7021.785611 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7021.785611 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5063185 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 195793 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4609637 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49643 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5064887 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 196421 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4608715 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49903 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8256 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 199856 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 430863 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8275 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 201573 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 431249 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 189917 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15760.362755 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1051721 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 205349 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.121627 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2533057390500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4796.141133 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.055492 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.249384 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 825.564654 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2172.411955 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7947.940138 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.292733 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001041 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000076 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.050388 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132594 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485104 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.961936 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8428 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6994 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2154 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2511 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3763 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2597 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1568 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2829 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.514404 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426880 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21502320 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21502320 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29274 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7085 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535244 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 196892 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 768495 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 291031 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 291031 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2209 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2209 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1205 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1205 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122716 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 122716 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29274 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7085 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 535244 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 319608 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 891211 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29274 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7085 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 535244 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 319608 # number of overall hits -system.cpu1.l2cache.overall_hits::total 891211 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 364 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 158 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11361 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 60780 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 72663 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20588 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 20588 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13188 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 13188 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25387 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 25387 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 364 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 158 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 11361 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 86167 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 98050 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 364 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 158 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 11361 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 86167 # number of overall misses -system.cpu1.l2cache.overall_misses::total 98050 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8462000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3365000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344449975 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612650155 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1968927130 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 357562229 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 357562229 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267838079 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267838079 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1192000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1192000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1149303620 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1149303620 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8462000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3365000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344449975 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2761953775 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3118230750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8462000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3365000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344449975 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2761953775 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3118230750 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29638 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7243 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546605 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257672 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 841158 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 291033 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 291033 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22797 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 22797 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14393 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 14393 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148103 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 148103 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29638 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7243 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 546605 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 405775 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 989261 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29638 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7243 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 546605 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 405775 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 989261 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.021814 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020785 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235881 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.086384 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.903101 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.903101 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.916279 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.916279 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171414 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171414 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.021814 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020785 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212352 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.099114 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.021814 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020785 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212352 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.099114 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21297.468354 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30318.631723 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26532.579056 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27096.694741 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17367.506752 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17367.506752 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20309.226494 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.226494 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 596000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 596000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45271.344389 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45271.344389 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31802.455380 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31802.455380 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 8115 # number of cycles access was blocked +system.cpu1.l2cache.tags.replacements 190012 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15761.494789 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1049012 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 205401 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.107142 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2533064784000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4779.201022 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.066276 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030051 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 839.580286 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2141.602652 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7985.014503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.291699 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000859 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.051244 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.130713 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.487367 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.962005 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8393 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6988 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2144 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2546 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3703 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2618 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1697 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2673 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.512268 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426514 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21490349 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21490349 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29593 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7243 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535438 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 196668 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 768942 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 290105 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 290105 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2163 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2163 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1236 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1236 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122721 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 122721 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29593 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7243 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 535438 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 319389 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 891663 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29593 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7243 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 535438 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 319389 # number of overall hits +system.cpu1.l2cache.overall_hits::total 891663 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 361 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 143 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11420 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 60562 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 72486 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20521 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 20521 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13163 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 13163 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25394 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 25394 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 361 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 143 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 11420 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 85956 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 97880 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 361 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 143 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 11420 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 85956 # number of overall misses +system.cpu1.l2cache.overall_misses::total 97880 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8348750 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3077500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344518477 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1610493915 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1966438642 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 355504452 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 355504452 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267510078 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267510078 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1281000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1281000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1148633604 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1148633604 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8348750 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3077500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344518477 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2759127519 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3115072246 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8348750 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3077500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344518477 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2759127519 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3115072246 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29954 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7386 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546858 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257230 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 841428 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 290106 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 290106 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22684 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 22684 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14399 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 14399 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148115 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 148115 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29954 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7386 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 546858 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 405345 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 989543 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29954 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7386 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 546858 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 405345 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 989543 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019361 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020883 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235439 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.086146 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.904646 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.904646 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.914161 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.914161 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171448 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171448 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019361 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020883 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212056 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.098914 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019361 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020883 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212056 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.098914 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21520.979021 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30167.992732 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26592.482332 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27128.530227 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17323.934116 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17323.934116 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20322.880650 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20322.880650 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45232.480271 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45232.480271 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21520.979021 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30167.992732 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32099.301026 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31825.421394 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21520.979021 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30167.992732 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32099.301026 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31825.421394 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 8171 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 442 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 441 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.359729 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.528345 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 108849 # number of writebacks -system.cpu1.l2cache.writebacks::total 108849 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 108610 # number of writebacks +system.cpu1.l2cache.writebacks::total 108610 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2808 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 143 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 2953 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1573 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 1573 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2944 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 155 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 3100 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1588 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 1588 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2808 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1716 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 4526 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2944 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1743 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 4688 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2808 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1716 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 4526 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 363 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 157 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8553 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60637 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 69710 # number of ReadReq MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 199848 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20588 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20588 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13188 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13188 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23814 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 23814 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 363 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 157 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8553 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84451 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 93524 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 363 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 157 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8553 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84451 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 293372 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2254500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 234181256 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1184058953 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1426398709 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10843374528 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 344645957 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 344645957 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188520557 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188520557 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 996000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 996000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 690789082 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 690789082 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2254500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 234181256 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1874848035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2117187791 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2254500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 234181256 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1874848035 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 12960562319 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4572000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174823243259 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174827815259 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29484635658 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29484635658 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4572000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204307878917 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204312450917 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.235326 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082874 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2944 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1743 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 4688 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 360 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 143 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8476 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60407 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 69386 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 201557 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 201557 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20521 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20521 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13163 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13163 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23806 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 23806 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 360 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 143 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8476 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84213 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 93192 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 360 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 143 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8476 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84213 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 201557 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 294749 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2076500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 233530753 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1183485205 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1424904708 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10818711595 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10818711595 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 343673223 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 343673223 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188113563 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188113563 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1071000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1071000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 694199615 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 694199615 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2076500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 233530753 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1877684820 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2119104323 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2076500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 233530753 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1877684820 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10818711595 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 12937815918 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4830750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174824022755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174828853505 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29482934435 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29482934435 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4830750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204306957190 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204311787940 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.234837 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082462 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.903101 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.903101 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.916279 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916279 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160794 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160794 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094539 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.904646 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.904646 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.914161 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914161 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160726 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160726 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.207756 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094177 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.207756 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29007.687999 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29007.687999 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22637.908890 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 44177.911726 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.297864 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19591.855331 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20535.910818 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.692707 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.692707 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16747.391599 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16747.391599 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14291.085847 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14291.085847 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29160.699614 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29160.699614 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22296.852267 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22739.122704 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22296.852267 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.692707 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43894.350508 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2972,190 +2961,190 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 381661 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940978 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94117 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 94117 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93451 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12063851 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12063851 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12088353 # number of overall hits -system.cpu1.dcache.overall_hits::total 12088353 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 362275 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 362275 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 967298 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 967298 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47536 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14955 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14395 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1329573 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1377109 # number of overall misses -system.cpu1.dcache.overall_misses::total 1377109 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4296873688 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 332075324 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 19924363324 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7567904 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5825520 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5825520 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 72038 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109072 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 109072 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107846 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 13393424 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 13465462 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047870 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166045 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137111 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102270 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency +system.cpu1.dcache.tags.replacements 381157 # number of replacements +system.cpu1.dcache.tags.tagsinuse 482.358158 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12336025 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 381566 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 32.329990 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70967583500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.358158 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.942106 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.942106 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 27772556 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 27772556 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7207091 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7207091 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4859664 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4859664 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24710 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 24710 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94182 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 94182 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93506 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 93506 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12066755 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12066755 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12091465 # number of overall hits +system.cpu1.dcache.overall_hits::total 12091465 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 361330 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 361330 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 966559 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 966559 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47195 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 47195 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14954 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14954 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14399 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 14399 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1327889 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1327889 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1375084 # number of overall misses +system.cpu1.dcache.overall_misses::total 1375084 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4284258220 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4284258220 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15637986446 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 15637986446 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254935748 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 254935748 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 331661328 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 331661328 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1371000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1371000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 19922244666 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 19922244666 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 19922244666 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 19922244666 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7568421 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7568421 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5826223 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5826223 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 71905 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 71905 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109136 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 109136 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107905 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 107905 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 13394644 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 13394644 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 13466549 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 13466549 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047742 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.047742 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.165898 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.165898 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.656352 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.656352 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137022 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137022 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133441 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133441 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099136 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.099136 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102111 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.102111 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11856.912573 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11856.912573 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16179.029367 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16179.029367 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17047.997058 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17047.997058 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23033.636225 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23033.636225 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15002.944272 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15002.944272 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14488.020125 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14488.020125 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 5063 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 2164841 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 227 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 93890 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.303965 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 23.057205 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks -system.cpu1.dcache.writebacks::total 291033 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 290106 # number of writebacks +system.cpu1.dcache.writebacks::total 290106 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147611 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 147611 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 796581 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 796581 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1422 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1422 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 944192 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 944192 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 944192 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 944192 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213719 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 213719 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 169978 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 169978 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30150 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 30150 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13532 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13532 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 14399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 383697 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 383697 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 413847 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 413847 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2234589083 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2234589083 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2566083982 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2566083982 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 631981244 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 631981244 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208947501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208947501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 301752672 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 301752672 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1311000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1311000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4800673065 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4800673065 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5432654309 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5432654309 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183654680990 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183654680990 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50890148887 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50890148887 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234544829877 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234544829877 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028238 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028238 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029175 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029175 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.419303 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.419303 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123992 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123992 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133441 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133441 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028646 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030731 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030731 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10455.734319 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10455.734319 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15096.565332 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15096.565332 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20961.235290 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20961.235290 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15440.991797 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15440.991797 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20956.501979 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20956.501979 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12511.625228 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12511.625228 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13127.204762 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13127.204762 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -3179,18 +3168,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735774629169 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1735774629169 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735774629169 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1735774629169 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42920 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50586 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |