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authorSteve Reinhardt <steve.reinhardt@amd.com>2014-07-19 19:04:58 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2014-07-19 19:04:58 -0700
commit040fa23d01109c68d194d2517df777844e4e2f13 (patch)
tree822b7da72458db435480c20c1a3448f6158c62aa
parent06bb6a473157a204bb7e77ea28e618aa08d2d811 (diff)
downloadgem5-040fa23d01109c68d194d2517df777844e4e2f13.tar.xz
stats: update for syscall DPRINTF change
Only printing one rather than two args for the ignored syscall warning means the count of register accesses has changed on a few runs. Oddly only Alpha Tru64 seems to have any ignored syscalls in the regression tests.
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini14
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr2
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt12
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini14
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr4
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout4
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt12
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini14
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr2
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt12
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini14
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr2
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt12
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini14
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr2
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini14
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt12
24 files changed, 133 insertions, 71 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index f722ba576..536d6ad31 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -37,7 +37,9 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -615,9 +617,19 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
index abe1622a9..664365742 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
@@ -48,4 +48,4 @@ Writing to chair.cook.ppm
12 8 14
13 8 14
14 8 14
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 9a57c805e..5f8084c1c 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 11:54:16
+gem5 compiled Jul 19 2014 12:27:06
+gem5 started Jul 19 2014 12:27:28
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index a85c15115..35136e25d 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.072880 # Nu
sim_ticks 72880000500 # Number of ticks simulated
final_tick 72880000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 218596 # Simulator instruction rate (inst/s)
-host_op_rate 218596 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42418396 # Simulator tick rate (ticks/s)
-host_mem_usage 228344 # Number of bytes of host memory used
-host_seconds 1718.12 # Real time elapsed on the host
+host_inst_rate 219272 # Simulator instruction rate (inst/s)
+host_op_rate 219272 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42549566 # Simulator tick rate (ticks/s)
+host_mem_usage 229100 # Number of bytes of host memory used
+host_seconds 1712.83 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -575,7 +575,7 @@ system.cpu.cpi 0.388098 # CP
system.cpu.cpi_total 0.388098 # CPI: Total CPI of All Threads
system.cpu.ipc 2.576666 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.576666 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 400324800 # number of integer regfile reads
+system.cpu.int_regfile_reads 400324799 # number of integer regfile reads
system.cpu.int_regfile_writes 170964393 # number of integer regfile writes
system.cpu.fp_regfile_reads 157088507 # number of floating regfile reads
system.cpu.fp_regfile_writes 104631166 # number of floating regfile writes
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index fac3ae4a0..a624ec61c 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -37,7 +37,9 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -615,9 +617,19 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
index b38cab2f9..cf5d2b5cc 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
@@ -2,5 +2,5 @@ warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(0, 1, ...)
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+warn: ignoring syscall sigprocmask(1, ...)
+warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index e5189014f..9bffb3068 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 21:27:33
+gem5 compiled Jul 19 2014 12:27:06
+gem5 started Jul 19 2014 12:27:27
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index ea32f292f..c36f62fc3 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.635929 # Nu
sim_ticks 635929494500 # Number of ticks simulated
final_tick 635929494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 162504 # Simulator instruction rate (inst/s)
-host_op_rate 162504 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56685894 # Simulator tick rate (ticks/s)
-host_mem_usage 228544 # Number of bytes of host memory used
-host_seconds 11218.48 # Real time elapsed on the host
+host_inst_rate 181383 # Simulator instruction rate (inst/s)
+host_op_rate 181383 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63271586 # Simulator tick rate (ticks/s)
+host_mem_usage 229300 # Number of bytes of host memory used
+host_seconds 10050.79 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -602,7 +602,7 @@ system.cpu.cpi 0.697657 # CP
system.cpu.cpi_total 0.697657 # CPI: Total CPI of All Threads
system.cpu.ipc 1.433369 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.433369 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2650222632 # number of integer regfile reads
+system.cpu.int_regfile_reads 2650222630 # number of integer regfile reads
system.cpu.int_regfile_writes 1504597172 # number of integer regfile writes
system.cpu.fp_regfile_reads 79149378 # number of floating regfile reads
system.cpu.fp_regfile_writes 52661639 # number of floating regfile writes
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 2fdef1249..e46a676eb 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -37,7 +37,9 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -615,9 +617,19 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
index 506aa6e28..de77515a1 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
@@ -2,4 +2,4 @@ warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index 6187ab612..3accfc0e2 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 12:22:04
+gem5 compiled Jul 19 2014 12:27:06
+gem5 started Jul 19 2014 12:27:28
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index b325b70f4..356c37c90 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.024221 # Nu
sim_ticks 24220559500 # Number of ticks simulated
final_tick 24220559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 197323 # Simulator instruction rate (inst/s)
-host_op_rate 197323 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 60047490 # Simulator tick rate (ticks/s)
-host_mem_usage 230944 # Number of bytes of host memory used
-host_seconds 403.36 # Real time elapsed on the host
+host_inst_rate 196594 # Simulator instruction rate (inst/s)
+host_op_rate 196594 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59825545 # Simulator tick rate (ticks/s)
+host_mem_usage 231620 # Number of bytes of host memory used
+host_seconds 404.85 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -606,7 +606,7 @@ system.cpu.cpi 0.608620 # CP
system.cpu.cpi_total 0.608620 # CPI: Total CPI of All Threads
system.cpu.ipc 1.643062 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.643062 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 116607972 # number of integer regfile reads
+system.cpu.int_regfile_reads 116607971 # number of integer regfile reads
system.cpu.int_regfile_writes 57833573 # number of integer regfile writes
system.cpu.fp_regfile_reads 254535 # number of floating regfile reads
system.cpu.fp_regfile_writes 240366 # number of floating regfile writes
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index b1e14ff22..a124b2ba9 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -37,7 +37,9 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -615,9 +617,19 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
index 506aa6e28..de77515a1 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
@@ -2,4 +2,4 @@ warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 5b5bf25c6..c56412480 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 16:50:46
+gem5 compiled Jul 19 2014 12:27:06
+gem5 started Jul 19 2014 12:27:27
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index e324bc13d..a090e3fd8 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.679350 # Nu
sim_ticks 679349778000 # Number of ticks simulated
final_tick 679349778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 165098 # Simulator instruction rate (inst/s)
-host_op_rate 165098 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64606302 # Simulator tick rate (ticks/s)
-host_mem_usage 222340 # Number of bytes of host memory used
-host_seconds 10515.22 # Real time elapsed on the host
+host_inst_rate 176355 # Simulator instruction rate (inst/s)
+host_op_rate 176355 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69011357 # Simulator tick rate (ticks/s)
+host_mem_usage 223060 # Number of bytes of host memory used
+host_seconds 9844.03 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -615,7 +615,7 @@ system.cpu.cpi 0.782641 # CP
system.cpu.cpi_total 0.782641 # CPI: Total CPI of All Threads
system.cpu.ipc 1.277725 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.277725 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3354502671 # number of integer regfile reads
+system.cpu.int_regfile_reads 3354502670 # number of integer regfile reads
system.cpu.int_regfile_writes 1955490145 # number of integer regfile writes
system.cpu.fp_regfile_reads 31250 # number of floating regfile reads
system.cpu.fp_regfile_writes 519 # number of floating regfile writes
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 104ffdb52..91fb4fb7f 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -37,7 +37,9 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -615,9 +617,19 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
index 506aa6e28..de77515a1 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
@@ -2,4 +2,4 @@ warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 2cc52ce3f..f7d4d117a 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 12:55:52
+gem5 compiled Jul 19 2014 12:27:06
+gem5 started Jul 19 2014 12:27:28
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 22a3b525f..35ce90696 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.023058 # Nu
sim_ticks 23058360500 # Number of ticks simulated
final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 185322 # Simulator instruction rate (inst/s)
-host_op_rate 185322 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50763012 # Simulator tick rate (ticks/s)
-host_mem_usage 226392 # Number of bytes of host memory used
-host_seconds 454.24 # Real time elapsed on the host
+host_inst_rate 185744 # Simulator instruction rate (inst/s)
+host_op_rate 185744 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50878767 # Simulator tick rate (ticks/s)
+host_mem_usage 227216 # Number of bytes of host memory used
+host_seconds 453.20 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -575,7 +575,7 @@ system.cpu.cpi 0.547837 # CP
system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads
system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 130779467 # number of integer regfile reads
+system.cpu.int_regfile_reads 130779466 # number of integer regfile reads
system.cpu.int_regfile_writes 71543363 # number of integer regfile writes
system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads
system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 5d14be284..a04bfcdcc 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -37,7 +37,9 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -615,9 +617,19 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
index 62976a831..025ac53d5 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
@@ -1,3 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 757b668d6..f39993dfb 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 10:38:16
+gem5 compiled Jul 19 2014 12:27:06
+gem5 started Jul 19 2014 12:27:28
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 827c29bcd..477ffe800 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu
sim_ticks 11975500 # Number of ticks simulated
final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28986 # Simulator instruction rate (inst/s)
-host_op_rate 28981 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 145369893 # Simulator tick rate (ticks/s)
-host_mem_usage 220536 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 10130 # Simulator instruction rate (inst/s)
+host_op_rate 10129 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50814142 # Simulator tick rate (ticks/s)
+host_mem_usage 221260 # Number of bytes of host memory used
+host_seconds 0.24 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -573,7 +573,7 @@ system.cpu.cpi 10.034353 # CP
system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads
system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 4676 # number of integer regfile reads
+system.cpu.int_regfile_reads 4675 # number of integer regfile reads
system.cpu.int_regfile_writes 2829 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads