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| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-08-12 14:11:45 +0100 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-08-12 14:11:45 +0100 |
| commit | 080d4e08d627b5b726afec71d38370373b7376c5 (patch) | |
| tree | 5a0676effdf719cc3d3b0ca1319d70770cc78eb4 | |
| parent | a23e914519de16061340db62d7a5dfc2cc7d027e (diff) | |
| download | gem5-080d4e08d627b5b726afec71d38370373b7376c5.tar.xz | |
mem: Add snoop filter to SystemXBar by default
This patch changes the default behaviour of the SystemXBar, adding a
snoop filter. With the recent updates to the snoop filter allocation
behaviour this change no longer causes problems for the regressions
without caches.
Change-Id: Ibe0cd437b71b2ede9002384126553679acc69cc1
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
| -rw-r--r-- | configs/common/CacheConfig.py | 5 | ||||
| -rw-r--r-- | src/mem/XBar.py | 3 | ||||
| -rw-r--r-- | tests/configs/base_config.py | 7 |
3 files changed, 4 insertions, 11 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 8489e3231..52659e89d 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -162,11 +162,6 @@ def config_cache(options, system): else: system.cpu[i].connectAllPorts(system.membus) - # Add a snoop filter to the membus if there are caches above it - if (options.l2cache or options.caches) and \ - (system.membus.snoop_filter == NULL): - system.membus.snoop_filter = SnoopFilter() - return system # ExternalSlave provides a "port", but when that port connects to a cache, diff --git a/src/mem/XBar.py b/src/mem/XBar.py index 674f9262e..59f0d8d8d 100644 --- a/src/mem/XBar.py +++ b/src/mem/XBar.py @@ -153,6 +153,9 @@ class SystemXBar(CoherentXBar): response_latency = 2 snoop_response_latency = 4 + # Use a snoop-filter by default + snoop_filter = SnoopFilter(lookup_latency = 1) + # This specialisation of the coherent crossbar is to be considered # the point of coherency, as there are no (coherent) downstream # caches. diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index 185c00020..860b84fa4 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -126,9 +126,6 @@ class BaseSystem(object): cpu.createInterruptController() cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus, system.membus) - # System has caches before the membus -> add snoop filter - if sha_bus and system.membus.snoop_filter == NULL: - system.membus.snoop_filter = SnoopFilter() def init_kvm(self, system): """Do KVM-specific system initialization. @@ -152,9 +149,7 @@ class BaseSystem(object): self.init_kvm(system) sha_bus = self.create_caches_shared(system) - # System has caches before the membus -> add snoop filter - if sha_bus and system.membus.snoop_filter == NULL: - system.membus.snoop_filter = SnoopFilter() + for cpu in system.cpu: self.init_cpu(system, cpu, sha_bus) |