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authorAnthony Gutierrez <atgutier@umich.edu>2014-07-28 12:22:00 -0400
committerAnthony Gutierrez <atgutier@umich.edu>2014-07-28 12:22:00 -0400
commit0ac462459522771c7836f5f53e82c6a679c256ca (patch)
tree7c5b370bcb8f3ab8bec669e410ddc6a3393f6845
parentcbf417c71322de6aee0afd9ca11444f935c1cd80 (diff)
downloadgem5-0ac462459522771c7836f5f53e82c6a679c256ca.tar.xz
arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2
the Cortex-A15 has a random replacement policy for its L2 cache. see the Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache.
-rw-r--r--configs/common/O3_ARM_v7a.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index 0202d19e4..5a94438d7 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -189,4 +189,4 @@ class O3_ARM_v7aL2(BaseCache):
prefetch_on_access = 'true'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
-
+ tags = RandomRepl()