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authorKorey Sewell <ksewell@umich.edu>2010-01-31 18:25:13 -0500
committerKorey Sewell <ksewell@umich.edu>2010-01-31 18:25:13 -0500
commit0e96798fe0a56936f8590dbd301f2b07a1850e22 (patch)
treeffa02a11f4812012b8d3dd4abd6f71d933e19999
parent7b3b362ba5d2690324abd58c883fd1d5fe4dc767 (diff)
downloadgem5-0e96798fe0a56936f8590dbd301f2b07a1850e22.tar.xz
configs/inorder: add options for switch-on-miss to inorder cpu
-rw-r--r--src/cpu/inorder/InOrderCPU.py5
-rw-r--r--src/cpu/inorder/cpu.cc11
-rw-r--r--src/cpu/inorder/cpu.hh10
3 files changed, 24 insertions, 2 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index a0b0466a7..d6db346d4 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -30,10 +30,15 @@ from m5.params import *
from m5.proxy import *
from BaseCPU import BaseCPU
+class ThreadModel(Enum):
+ vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
+
class InOrderCPU(BaseCPU):
type = 'InOrderCPU'
activity = Param.Unsigned(0, "Initial count")
+ threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
+
cachePorts = Param.Unsigned(2, "Cache Ports")
stageWidth = Param.Unsigned(1, "Stage width")
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 38f6b4eed..a1e6c9c86 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -197,7 +197,7 @@ InOrderCPU::InOrderCPU(Params *params)
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing),
numVirtProcs(1)
-{
+{
ThreadID active_threads;
cpu_params = params;
@@ -216,6 +216,15 @@ InOrderCPU::InOrderCPU(Params *params)
"in your InOrder implementation or "
"edit your workload size.");
}
+
+ if (active_threads > 1) {
+ threadModel = (InOrderCPU::ThreadModel) params->threadModel;
+ } else {
+ threadModel = Single;
+ }
+
+
+
#endif
// Bind the fetch & data ports from the resource pool.
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 463ca5445..804054f8c 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -100,6 +100,15 @@ class InOrderCPU : public BaseCPU
/** Type of core that this is */
std::string coreType;
+ // Only need for SE MODE
+ enum ThreadModel {
+ Single,
+ SMT,
+ SwitchOnCacheMiss
+ };
+
+ ThreadModel threadModel;
+
int readCpuId() { return cpu_id; }
void setCpuId(int val) { cpu_id = val; }
@@ -117,7 +126,6 @@ class InOrderCPU : public BaseCPU
/** Overall CPU status. */
Status _status;
-
private:
/** Define TickEvent for the CPU */
class TickEvent : public Event