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authorSteve Reinhardt <steve.reinhardt@amd.com>2016-02-06 17:21:20 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2016-02-06 17:21:20 -0800
commit2d91e741e8ffc8ae3d40f1e849db87e69af7bfa9 (patch)
tree7516d86052480e28009bb772083ddd7b9eb72415
parent4e65e25e257f30f2185bc4c4bd06e5b1fdb9688d (diff)
downloadgem5-2d91e741e8ffc8ae3d40f1e849db87e69af7bfa9.tar.xz
x86: create function to check miscreg validity
In the process of trying to get rid of an '== false' comparison, it became apparent that a slightly more involved solution was needed. Split this out into its own changeset since it's not a totally trivial local change like the others.
-rw-r--r--src/arch/x86/isa.cc16
-rw-r--r--src/arch/x86/regs/misc.hh11
-rw-r--r--src/arch/x86/utility.cc6
3 files changed, 14 insertions, 19 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 213a9e2e3..ad7248841 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -129,13 +129,7 @@ ISA::readMiscRegNoEffect(int miscReg) const
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
// attempt to read them directly.
- assert(miscReg >= MISCREG_CR0 &&
- miscReg < NUM_MISCREGS &&
- miscReg != MISCREG_CR1 &&
- !(miscReg > MISCREG_CR4 &&
- miscReg < MISCREG_CR8) &&
- !(miscReg > MISCREG_CR8 &&
- miscReg <= MISCREG_CR15));
+ assert(isValidMiscReg(miscReg));
return regVal[miscReg];
}
@@ -162,13 +156,7 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
// attempt to write to them directly.
- assert(miscReg >= MISCREG_CR0 &&
- miscReg < NUM_MISCREGS &&
- miscReg != MISCREG_CR1 &&
- !(miscReg > MISCREG_CR4 &&
- miscReg < MISCREG_CR8) &&
- !(miscReg > MISCREG_CR8 &&
- miscReg <= MISCREG_CR15));
+ assert(isValidMiscReg(miscReg));
HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
switch (miscReg) {
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 77f4e1bcd..48f7d974d 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -101,7 +101,7 @@ namespace X86ISA
enum MiscRegIndex
{
// Control registers
- // Most of these are invalid.
+ // Most of these are invalid. See isValidMiscReg() below.
MISCREG_CR_BASE,
MISCREG_CR0 = MISCREG_CR_BASE,
MISCREG_CR1,
@@ -399,6 +399,15 @@ namespace X86ISA
NUM_MISCREGS
};
+ static inline bool
+ isValidMiscReg(int index)
+ {
+ return (index >= MISCREG_CR0 && index < NUM_MISCREGS &&
+ index != MISCREG_CR1 &&
+ !(index > MISCREG_CR4 && index < MISCREG_CR8) &&
+ !(index > MISCREG_CR8 && index <= MISCREG_CR15));
+ }
+
static inline MiscRegIndex
MISCREG_CR(int index)
{
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index cf6d2d910..cf3072348 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -217,11 +217,9 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
// need to be considered while copying state. That will likely not be
// true in the future.
for (int i = 0; i < NUM_MISCREGS; ++i) {
- if ( ( i != MISCREG_CR1 &&
- !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
- !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
+ if (!isValidMiscReg(i))
continue;
- }
+
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
}