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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-02-27 16:33:11 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-02-27 16:33:11 -0500 |
| commit | 31fc398f0641a9dcc9757520e9dc7fd2cce102fb (patch) | |
| tree | e398cf4520c7fe1e0f0088b40f5520aa6f80c68b | |
| parent | b6247c9ea7ddc459a076dddf5e5f330da0211c1e (diff) | |
| download | gem5-31fc398f0641a9dcc9757520e9dc7fd2cce102fb.tar.xz | |
Fixes so that it compiles properly. Still working on .py file issues.
SConscript:
Add Back memory to be built
mem/physical.hh:
Fix function declerations
python/m5/objects/BaseCPU.py:
Remove IL1 and DL1 params from the cpu object
--HG--
extra : convert_revision : 2f285dc626bc8d84d095def68e986fe7e6f3d8e9
| -rw-r--r-- | SConscript | 1 | ||||
| -rw-r--r-- | mem/physical.hh | 4 | ||||
| -rw-r--r-- | python/m5/objects/BaseCPU.py | 2 |
3 files changed, 3 insertions, 4 deletions
diff --git a/SConscript b/SConscript index 078b1e831..1c13a9307 100644 --- a/SConscript +++ b/SConscript @@ -91,6 +91,7 @@ base_sources = Split(''' cpu/static_inst.cc cpu/sampler/sampler.cc + mem/memory.cc mem/page_table.cc mem/physical.cc mem/port.cc diff --git a/mem/physical.hh b/mem/physical.hh index fb2d0d743..90515d7d1 100644 --- a/mem/physical.hh +++ b/mem/physical.hh @@ -70,9 +70,9 @@ class PhysicalMemory : public Memory std::map<std::string, MemoryPort*> memoryPortList; - Port * PhysicalMemory::getPort(const char *if_name); + virtual Port * getPort(const char *if_name); - Port * addPort(std::string portName); + virtual Port * addPort(std::string portName); int numPorts; diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index fac452285..e5e43022f 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -2,8 +2,6 @@ from m5 import * class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - icache = Param.BaseMem(NULL, "L1 instruction cache object") - dcache = Param.BaseMem(NULL, "L1 data cache object") if build_env['FULL_SYSTEM']: dtb = Param.AlphaDTB("Data TLB") |