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authorAli Saidi <Ali.Saidi@arm.com>2010-08-23 11:18:40 -0500
committerAli Saidi <Ali.Saidi@arm.com>2010-08-23 11:18:40 -0500
commit38cf6a164d7081f1a2f40ab210169681b4cd6929 (patch)
tree98f3a6f7b4fdbb3f271f4a5b59302b85e6caa821
parentb7b2eae6fa56a5b2923f8aa8cd7b5425d10163df (diff)
downloadgem5-38cf6a164d7081f1a2f40ab210169681b4cd6929.tar.xz
ARM: Implement some more misc registers
-rw-r--r--src/arch/arm/isa.cc23
-rw-r--r--src/arch/arm/isa/formats/misc.isa3
-rw-r--r--src/arch/arm/miscregs.cc48
-rw-r--r--src/arch/arm/miscregs.hh29
4 files changed, 86 insertions, 17 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 17f95e57d..3a52919d4 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -212,6 +212,20 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
break;
case MISCREG_ID_PFR0:
return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM
+ case MISCREG_ID_MMFR0:
+ return 0x03; //VMSAz7
+ case MISCREG_CTR:
+ return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
+ case MISCREG_ACTLR:
+ warn("Not doing anything for miscreg ACTLR\n");
+ break;
+ case MISCREG_PMCR:
+ case MISCREG_PMCCNTR:
+ case MISCREG_PMSELR:
+ warn("Not doing anyhting for read to miscreg %s\n",
+ miscRegName[misc_reg]);
+ break;
+
}
return readMiscRegNoEffect(misc_reg);
}
@@ -394,6 +408,15 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
case MISCREG_DTLBIASID:
tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
return;
+ case MISCREG_ACTLR:
+ warn("Not doing anything for write of miscreg ACTLR\n");
+ break;
+ case MISCREG_PMCR:
+ case MISCREG_PMCCNTR:
+ case MISCREG_PMSELR:
+ warn("Not doing anything for write to miscreg %s\n",
+ miscRegName[misc_reg]);
+ break;
case MISCREG_V2PCWPR:
case MISCREG_V2PCWPW:
case MISCREG_V2PCWUR:
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 2801ebedf..884d93066 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -113,6 +113,9 @@ let {{
case MISCREG_DCCMVAC:
return new WarnUnimplemented(
isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
+ case MISCREG_DCCMVAU:
+ return new WarnUnimplemented(
+ isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
case MISCREG_CP15ISB:
return new WarnUnimplemented(
isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 776ed94c3..fd861befc 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -341,24 +341,48 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
}
break;
case 9:
- if (opc1 >= 0 && opc1 <= 7) {
+ if (opc1 == 0) {
switch (crm) {
- case 0:
- case 1:
- case 2:
- case 5:
- case 6:
- case 7:
- case 8:
- //Reserved for Branch Predictor, Cache and TCM operations
case 12:
+ switch (opc2) {
+ case 0:
+ return MISCREG_PMCR;
+ case 1:
+ return MISCREG_PMCNTENSET;
+ case 2:
+ return MISCREG_PMCNTENCLR;
+ case 3:
+ return MISCREG_PMOVSR;
+ case 4:
+ return MISCREG_PMSWINC;
+ case 5:
+ return MISCREG_PMSELR;
+ case 6:
+ return MISCREG_PMCEID0;
+ case 7:
+ return MISCREG_PMCEID1;
+ }
case 13:
+ switch (opc2) {
+ case 0:
+ return MISCREG_PMCCNTR;
+ case 1:
+ return MISCREG_PMC_OTHER;
+ case 2:
+ return MISCREG_PMXEVCNTR;
+ }
case 14:
- case 15:
- // Reserved for Performance monitors
- break;
+ switch (opc2) {
+ case 0:
+ return MISCREG_PMUSERENR;
+ case 1:
+ return MISCREG_PMINTENSET;
+ case 2:
+ return MISCREG_PMINTENCLR;
+ }
}
}
+ //Reserved for Branch Predictor, Cache and TCM operations
break;
case 10:
if (opc1 == 0) {
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 267626e74..86a11d508 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -147,12 +147,27 @@ namespace ArmISA
MISCREG_V2POWPW,
MISCREG_V2POWUR,
MISCREG_V2POWUW,
+ MISCREG_ID_MMFR0,
+ MISCREG_ACTLR,
+ MISCREG_PMCR,
+ MISCREG_PMCCNTR,
+ MISCREG_PMCNTENSET,
+ MISCREG_PMCNTENCLR,
+ MISCREG_PMOVSR,
+ MISCREG_PMSWINC,
+ MISCREG_PMSELR,
+ MISCREG_PMCEID0,
+ MISCREG_PMCEID1,
+ MISCREG_PMC_OTHER,
+ MISCREG_PMXEVCNTR,
+ MISCREG_PMUSERENR,
+ MISCREG_PMINTENSET,
+ MISCREG_PMINTENCLR,
MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
MISCREG_ID_PFR1,
MISCREG_ID_DFR0,
MISCREG_ID_AFR0,
- MISCREG_ID_MMFR0,
MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2,
MISCREG_ID_MMFR3,
@@ -163,7 +178,6 @@ namespace ArmISA
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
MISCREG_AIDR,
- MISCREG_ACTLR,
MISCREG_ADFSR,
MISCREG_AIFSR,
MISCREG_DCIMVAC,
@@ -210,12 +224,17 @@ namespace ArmISA
"scr", "sder", "par",
"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
"v2powpr", "v2powpw", "v2powur", "v2powuw",
- // Unimplemented below
+ "id_mmfr0","actlr", "pmcr", "pmcntr",
+ "pmcntenset", "pmcntenclr", "pmovsr",
+ "pmswinc", "pmselr", "pmceid0",
+ "pmceid1", "pmc_other", "pmxevcntr",
+ "pmuserenr", "pmintenset", "pmintenclr",
+ // Unimplemented below
"tcmtr",
"id_pfr1", "id_dfr0", "id_afr0",
- "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
+ "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
- "aidr", "actlr",
+ "aidr",
"adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",
"dccmvau",