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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
| commit | 44759669aa3633d96cbfd722c1f135f2c69d62f0 (patch) | |
| tree | 6ec1bfd3849f357c2549d8d848d0e79b4e3acaf3 | |
| parent | 9e32ff3491b3af115896798af3fd8c3606aac50f (diff) | |
| download | gem5-44759669aa3633d96cbfd722c1f135f2c69d62f0.tar.xz | |
ARM: Implement the VFP version of vadd.
| -rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 20 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 25 |
2 files changed, 44 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 29b1470e9..95be69ca6 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -510,7 +510,25 @@ let {{ return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst); case 0x3: if ((opc3 & 0x1) == 0) { - return new WarnUnimplemented("vadd", machInst); + uint32_t vd; + uint32_t vm; + uint32_t vn; + if (bits(machInst, 8) == 0) { + vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); + vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); + vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); + return new VaddS(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } else { + vd = (bits(machInst, 22) << 5) | + (bits(machInst, 15, 12) << 1); + vm = (bits(machInst, 5) << 5) | + (bits(machInst, 3, 0) << 1); + vn = (bits(machInst, 7) << 5) | + (bits(machInst, 19, 16) << 1); + return new VaddD(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } } else { return new WarnUnimplemented("vsub", machInst); } diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 56edb23f2..80be3d3c3 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -306,4 +306,29 @@ let {{ header_output += RegRegOpDeclare.subst(vabsDIop); decoder_output += RegRegOpConstructor.subst(vabsDIop); exec_output += PredOpExecute.subst(vabsDIop); + + vaddSCode = ''' + FpDest = FpOp1 + FpOp2; + ''' + vaddSIop = InstObjParams("vadds", "VaddS", "RegRegRegOp", + { "code": vaddSCode, + "predicate_test": predicateTest }, []) + header_output += RegRegRegOpDeclare.subst(vaddSIop); + decoder_output += RegRegRegOpConstructor.subst(vaddSIop); + exec_output += PredOpExecute.subst(vaddSIop); + + vaddDCode = ''' + IntDoubleUnion cOp1, cOp2, cDest; + cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); + cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); + cDest.fp = cOp1.fp + cOp2.fp; + FpDestP0.uw = cDest.bits; + FpDestP1.uw = cDest.bits >> 32; + ''' + vaddDIop = InstObjParams("vaddd", "VaddD", "RegRegRegOp", + { "code": vaddDCode, + "predicate_test": predicateTest }, []) + header_output += RegRegRegOpDeclare.subst(vaddDIop); + decoder_output += RegRegRegOpConstructor.subst(vaddDIop); + exec_output += PredOpExecute.subst(vaddDIop); }}; |