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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-12-16 03:48:13 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-12-16 03:48:13 -0500 |
commit | 71909a50de2dd5154622c936179d97ec5220f872 (patch) | |
tree | a563ba58ccf8596dc51aaf98c82ad6c6f71deec6 | |
parent | b7ea470a976febd1fad8509a3b6b912672ba4ca3 (diff) | |
download | gem5-71909a50de2dd5154622c936179d97ec5220f872.tar.xz |
CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
--HG--
extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
-rw-r--r-- | src/cpu/simple/atomic.cc | 12 | ||||
-rw-r--r-- | src/cpu/simple/base.cc | 1 | ||||
-rw-r--r-- | src/cpu/simple/timing.cc | 3 |
3 files changed, 10 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index aead5aada..4553c0ae2 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -79,12 +79,13 @@ void AtomicSimpleCPU::init() { BaseCPU::init(); + cpuId = tc->readCpuId(); #if FULL_SYSTEM for (int i = 0; i < threadContexts.size(); ++i) { ThreadContext *tc = threadContexts[i]; // initialize CPU, including PC - TheISA::initCPU(tc, tc->readCpuId()); + TheISA::initCPU(tc, cpuId); } #endif if (hasPhysMemPort) { @@ -93,6 +94,9 @@ AtomicSimpleCPU::init() physmemPort.getPeerAddressRanges(pmAddrList, snoop); physMemAddr = *pmAddrList.begin(); } + ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT + data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too + data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too } bool @@ -159,9 +163,6 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p) icachePort.snoopRangeSent = false; dcachePort.snoopRangeSent = false; - ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT - data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too - data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too } @@ -240,6 +241,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) } assert(threadContexts.size() == 1); cpuId = tc->readCpuId(); + ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT + data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too + data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too } diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index ad7b14be3..367f38b89 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -91,7 +91,6 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p) threadContexts.push_back(tc); - cpuId = tc->readCpuId(); fetchOffset = 0; stayAtPC = false; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 8d6a169ab..2f3ee5c73 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -57,12 +57,13 @@ void TimingSimpleCPU::init() { BaseCPU::init(); + cpuId = tc->readCpuId(); #if FULL_SYSTEM for (int i = 0; i < threadContexts.size(); ++i) { ThreadContext *tc = threadContexts[i]; // initialize CPU, including PC - TheISA::initCPU(tc, tc->readCpuId()); + TheISA::initCPU(tc, cpuId); } #endif } |