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authorJoel Hestness <hestness@cs.wisc.edu>2012-09-12 21:42:57 -0500
committerJoel Hestness <hestness@cs.wisc.edu>2012-09-12 21:42:57 -0500
commit90dd745ff61df35b5144ae40be7e6f16dfce463c (patch)
treeb2eba7072e7d198e3891f7bb5c2ff9cb96e27f58
parent234fa4cf7ecd16350c1095830d26f94b2bfd3eb9 (diff)
downloadgem5-90dd745ff61df35b5144ae40be7e6f16dfce463c.tar.xz
se.py Ruby: Connect TLB walker ports
In order to ensure correct functionality of switch CPUs, the TLB walker ports must be connected to the Ruby system in x86 simulation. This fixes x86 assertion failures that the TLB walker ports are not connected during the CPU switch process.
-rw-r--r--configs/example/se.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/example/se.py b/configs/example/se.py
index 887e414ca..b60baf041 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -198,6 +198,9 @@ if options.ruby:
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
+ if buildEnv['TARGET_ISA'] == 'x86':
+ system.cpu[i].itb.walker.port = ruby_port.slave
+ system.cpu[i].dtb.walker.port = ruby_port.slave
else:
system.system_port = system.membus.slave
system.physmem.port = system.membus.master