configs: Update the DRAM sweep script to use PyTrafficGen

Instead of generating a text configuration, use the new Python-based
traffic generator.

Change-Id: I6fb88ec45b74bb87470aa265af18b5a2ff24c314
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11519
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 25 insertions, 33 deletions

diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 8380f74e3..10ef7486d 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2014-2015 ARM Limited
+# Copyright (c) 2014-2015, 2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,6 +37,7 @@
 
 from __future__ import print_function
 
+import math
 import optparse
 
 import m5
@@ -55,6 +56,11 @@ from common import MemConfig
 
 parser = optparse.OptionParser()
 
+dram_generators = {
+    "DRAM" : lambda x: x.createDram,
+    "DRAM_ROTATE" : lambda x: x.createDramRot,
+}
+
 # Use a single-channel DDR3-1600 x64 (8x8 topology) by default
 parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
                   choices=MemConfig.mem_names(),
@@ -67,7 +73,7 @@ parser.add_option("--rd_perc", type="int", default=100,
                   help = "Percentage of read commands")
 
 parser.add_option("--mode", type="choice", default="DRAM",
-                  choices=["DRAM", "DRAM_ROTATE"],
+                  choices=dram_generators.keys(),
                   help = "DRAM: Random traffic; \
                           DRAM_ROTATE: Traffic rotating across banks and ranks")
 
@@ -127,11 +133,6 @@ else:
 # short enough to avoid hitting a refresh
 period = 250000000
 
-# this is where we go off piste, and print the traffic generator
-# configuration that we will later use, crazy but it works
-cfg_file_name = "configs/dram/sweep.cfg"
-cfg_file = open(cfg_file_name, 'w')
-
 # stay in each state as long as the dump/reset period, use the entire
 # range, issue transactions of the right DRAM burst size, and match
 # the DRAM maximum bandwidth to ensure that it is saturated
@@ -159,32 +160,8 @@ max_addr = mem_range.end
 # enough
 max_stride = min(512, page_size)
 
-# now we create the state by iterating over the stride size from burst
-# size to the max stride, and from using only a single bank up to the
-# number of banks available
-nxt_state = 0
-for bank in range(1, nbr_banks + 1):
-    for stride_size in range(burst_size, max_stride + 1, burst_size):
-        cfg_file.write("STATE %d %d %s %d 0 %d %d "
-                       "%d %d %d %d %d %d %d %d %d\n" %
-                       (nxt_state, period, options.mode, options.rd_perc,
-                        max_addr, burst_size, itt, itt, 0, stride_size,
-                        page_size, nbr_banks, bank, options.addr_map,
-                        options.mem_ranks))
-        nxt_state = nxt_state + 1
-
-cfg_file.write("INIT 0\n")
-
-# go through the states one by one
-for state in range(1, nxt_state):
-    cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
-
-cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
-
-cfg_file.close()
-
 # create a traffic generator, and point it to the file we just created
-system.tgen = TrafficGen(config_file = cfg_file_name)
+system.tgen = PyTrafficGen()
 
 # add a communication monitor
 system.monitor = CommMonitor()
@@ -204,7 +181,22 @@ root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 m5.instantiate()
-m5.simulate(nxt_state * period)
+
+def trace():
+    generator = dram_generators[options.mode](system.tgen)
+    for bank in range(1, nbr_banks + 1):
+        for stride_size in range(burst_size, max_stride + 1, burst_size):
+            num_seq_pkts = int(math.ceil(float(stride_size) / burst_size))
+            yield generator(period,
+                            0, max_addr, burst_size, int(itt), int(itt),
+                            options.rd_perc, 0,
+                            num_seq_pkts, page_size, nbr_banks, bank,
+                            options.addr_map, options.mem_ranks)
+    yield system.tgen.createExit(0)
+
+system.tgen.start(trace())
+
+m5.simulate()
 
 print("DRAM sweep with burst: %d, banks: %d, max stride: %d" %
     (burst_size, nbr_banks, max_stride))