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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-21 09:53:37 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-21 12:09:19 +0000 |
| commit | c03e7b3d221a927ceda6fdb7dd65ccd1a0df1945 (patch) | |
| tree | aeab9d96533677d701d0e35fe8614321254cc4b1 | |
| parent | 5d442571eff5116551609ee7a3b63a3b9d27ff45 (diff) | |
| download | gem5-c03e7b3d221a927ceda6fdb7dd65ccd1a0df1945.tar.xz | |
cpu: Fix bug introduced by RequestPtr type change
Missing buffer allocation in mwaitAtomic.
Change-Id: Ifccb6df2427df8b0daac5ee6a99e5cca0b20825e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/cpu/base.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 1a497db9a..878e65551 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -318,7 +318,8 @@ BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) assert(tid < numThreads); AddressMonitor &monitor = addressMonitor[tid]; - RequestPtr req; + RequestPtr req = std::make_shared<Request>(); + Addr addr = monitor.vAddr; int block_size = cacheLineSize(); uint64_t mask = ~((uint64_t)(block_size - 1)); |