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| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-01 19:26:44 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-01 19:26:44 -0500 |
| commit | c21bf8e7aebe9157488f300edbf378d9a2d3cf71 (patch) | |
| tree | 2395aa1bbc4ed398c82edb0eb592bf18c5628068 | |
| parent | 13608a9b85a60982a9fa0ebee38a1d15c0ea5fc5 (diff) | |
| download | gem5-c21bf8e7aebe9157488f300edbf378d9a2d3cf71.tar.xz | |
Another pass at the prefetcher. Now it works with both miss and access reference streams.
Reworked how it is instattiated and how it communicates with other cache objects.
SConscript:
Compile all the prefetcher files
objects/BaseCache.mpy:
Add parameters for prefetcher
--HG--
extra : convert_revision : 2faa81c17673420ffae72a50a27e310d4c0f4135
| -rw-r--r-- | SConscript | 5 | ||||
| -rw-r--r-- | objects/BaseCache.mpy | 9 |
2 files changed, 11 insertions, 3 deletions
diff --git a/SConscript b/SConscript index 6fe99b314..444f71afe 100644 --- a/SConscript +++ b/SConscript @@ -164,7 +164,10 @@ base_sources = Split(''' mem/cache/miss/miss_queue.cc mem/cache/miss/mshr.cc mem/cache/miss/mshr_queue.cc - mem/cache/miss/prefetcher.cc + mem/cache/prefetch/base_prefetcher.cc + mem/cache/prefetch/prefetcher.cc + mem/cache/prefetch/stride_prefetcher.cc + mem/cache/prefetch/tagged_prefetcher.cc mem/cache/tags/base_tags.cc mem/cache/tags/cache_tags.cc mem/cache/tags/fa_lru.cc diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy index 314a4efda..cb3e56de6 100644 --- a/objects/BaseCache.mpy +++ b/objects/BaseCache.mpy @@ -36,7 +36,12 @@ simobj BaseCache(BaseMem): two_queue = Param.Bool(False, "whether the lifo should have two queue replacement") write_buffers = Param.Int(8, "number of write buffers") - use_prefetcher = Param.Bool(False, - "wheter you are using the hardware prefetcher") + prefetch_miss = Param.Bool(False, + "wheter you are using the hardware prefetcher from Miss stream") + prefetch_access = Param.Bool(False, + "wheter you are using the hardware prefetcher from Access stream") prefetcher_size = Param.Int(100, "Number of entries in the harware prefetch queue") + prefetch_past_page = Param.Bool(False, + "Allow prefetches to cross virtual page boundaries") + |