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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 01:57:34 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 01:57:34 -0800 |
| commit | f63c260d89591d8d57274bb37aea51dc7c093b8f (patch) | |
| tree | 1bf74575fd90f47266ddeac1aef5b7e332628cba | |
| parent | 43e9209c218daf506b6c2580e689e297c48e8f48 (diff) | |
| download | gem5-f63c260d89591d8d57274bb37aea51dc7c093b8f.tar.xz | |
ARM: Get rid of the Raddr operand.
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index ac7427dad..a4c404bd5 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -63,7 +63,6 @@ def operands {{ 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), - 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6), 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7), 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8), 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9), |