diff options
| author | Ciro Santilli <ciro.santilli@arm.com> | 2018-06-21 11:28:58 +0100 |
|---|---|---|
| committer | Ciro Santilli <ciro.santilli@arm.com> | 2018-07-17 11:28:23 +0000 |
| commit | ff52563a214c71fcd1e21e9f00ad839612032e3b (patch) | |
| tree | 7a4d266a371adaad34b23537d161ce9a12fed87b | |
| parent | 889fdb90d92180f9b0526ffdcf1690715ac8e715 (diff) | |
| download | gem5-ff52563a214c71fcd1e21e9f00ad839612032e3b.tar.xz | |
dev, arm: accept and ignore writes to GIC APRn registers
Otherwise the Linux kernel v4.17 boot fails with error:
Tried to write Gic cpu at offset 0xd0
Change-Id: Ie8063212c9e2b29e2e4766801b4b9538e9eccbf8
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11590
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/dev/arm/gic_pl390.cc | 8 | ||||
| -rw-r--r-- | src/dev/arm/gic_pl390.hh | 6 |
2 files changed, 12 insertions, 2 deletions
diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc index f918f7783..b0c4e99ee 100644 --- a/src/dev/arm/gic_pl390.cc +++ b/src/dev/arm/gic_pl390.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2013, 2015-2017 ARM Limited + * Copyright (c) 2010, 2013, 2015-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -602,6 +602,12 @@ Pl390::writeCpu(ContextID ctx, Addr daddr, uint32_t data) ctx, iar.ack_id, iar.cpu_id); break; } + case GICC_APR0: + case GICC_APR1: + case GICC_APR2: + case GICC_APR3: + warn("GIC APRn write ignored because not implemented: %#x\n", daddr); + break; default: panic("Tried to write Gic cpu at offset %#x\n", daddr); break; diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh index dc45d25d7..b4e880bf2 100644 --- a/src/dev/arm/gic_pl390.hh +++ b/src/dev/arm/gic_pl390.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2013, 2015-2017 ARM Limited + * Copyright (c) 2010, 2013, 2015-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -105,6 +105,10 @@ class Pl390 : public BaseGic, public BaseGicRegisters GICC_RPR = 0x14, // running priority GICC_HPPIR = 0x18, // highest pending interrupt GICC_ABPR = 0x1c, // aliased binary point + GICC_APR0 = 0xd0, // active priority register 0 + GICC_APR1 = 0xd4, // active priority register 1 + GICC_APR2 = 0xd8, // active priority register 2 + GICC_APR3 = 0xdc, // active priority register 3 GICC_IIDR = 0xfc, // cpu interface id register CPU_SIZE = 0xff |