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| author | Javier Cano-Cano <javier.cano555@gmail.com> | 2017-03-13 16:38:18 +0100 |
|---|---|---|
| committer | Javier Cano-Cano <javier.cano555@gmail.com> | 2017-04-05 21:30:47 +0000 |
| commit | 01bc2ea80d514abb5009869fc6b765208192906f (patch) | |
| tree | 97cfd8c00b76d96d0ecfef9de8f0fd75749ef273 | |
| parent | a8f1f9811c3fdb1cf59f6d37540ad40e4699561f (diff) | |
| download | gem5-01bc2ea80d514abb5009869fc6b765208192906f.tar.xz | |
ruby: Fix MOESI_CMP_directory for new DMA status changes.
Multiple outstanding DMA requests introduced new DMA states that didn't
be considered into slicc code. This patch implements the missed DMA state
changes on MOESI_CMP_directory protocol.
Change-Id: I700d441d76556b7e77e0d507904af6ec6ba59cc2
Signed-off-by: Michael LeBeane <michael.lebeane@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/2380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
| -rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dma.sm | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index ccc7f8790..b9da0d0dc 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -77,6 +77,7 @@ machine(MachineType:DMA, "DMA Controller") Tick clockEdge(); void set_tbe(TBE b); void unset_tbe(); + void wakeUpAllBuffers(); State getState(TBE tbe, Addr addr) { return cur_state; @@ -249,6 +250,13 @@ machine(MachineType:DMA, "DMA Controller") unset_tbe(); } + action(zz_stallAndWaitRequestQueue, "zz", desc="...") { + stall_and_wait(dmaRequestQueue_in, address); + } + + action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") { + wakeUpAllBuffers(); + } transition(READY, ReadRequest, BUSY_RD) { s_sendReadRequest; @@ -269,6 +277,7 @@ machine(MachineType:DMA, "DMA Controller") //u_updateAckCount; //o_checkForCompletion; p_popResponseQueue; + wkad_wakeUpAllDependents; } transition(BUSY_RD, All_Acks, READY) { @@ -276,6 +285,7 @@ machine(MachineType:DMA, "DMA Controller") //u_sendExclusiveUnblockToDir; w_deallocateTBE; p_popTriggerQueue; + wkad_wakeUpAllDependents; } transition(READY, WriteRequest, BUSY_WR) { @@ -301,5 +311,10 @@ machine(MachineType:DMA, "DMA Controller") u_sendExclusiveUnblockToDir; w_deallocateTBE; p_popTriggerQueue; + wkad_wakeUpAllDependents; + } + + transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) { + zz_stallAndWaitRequestQueue; } } |