Merge zizzer:/bk/newmem

into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 5fc80b28362c4acc4dee576f60296b81aea004f2

10 files changed, 135 insertions, 45 deletions

diff --git a/arch/alpha/system.cc b/arch/alpha/system.cc
index 21ffa350b..4234019cd 100644
--- a/arch/alpha/system.cc
+++ b/arch/alpha/system.cc
@@ -107,9 +107,9 @@ AlphaSystem::AlphaSystem(Params *p)
     if (consoleSymtab->findAddress("m5_rpb", addr)) {
         uint64_t data;
         data = htog(params()->system_type);
-        virtPort.write(addr, data);
+        virtPort.write(addr+0x50, data);
         data = htog(params()->system_rev);
-        virtPort.write(addr, data);
+        virtPort.write(addr+0x58, data);
     } else
         panic("could not find hwrpb\n");
 
diff --git a/configs/test/fs.py b/configs/test/fs.py
new file mode 100644
index 000000000..d2e5381f0
--- /dev/null
+++ b/configs/test/fs.py
@@ -0,0 +1,109 @@
+import os
+from SysPaths import *
+
+# Base for tests is directory containing this file.
+test_base = os.path.dirname(__file__)
+
+class BaseTsunami(Tsunami):
+    cchip = TsunamiCChip(pio_addr=0x801a0000000)
+    pchip = TsunamiPChip(pio_addr=0x80180000000)
+    pciconfig = PciConfigAll(pio_addr=0x801fe000000)
+    fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
+
+    fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
+    fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
+    fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
+    fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
+
+    fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
+
+    fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
+
+    fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
+    fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
+    fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
+    fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
+    fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
+    fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
+    fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
+    fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
+    fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
+    fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
+
+    fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
+    fake_ata1 = IsaFake(pio_addr=0x801fc000170)
+
+    fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
+    io = TsunamiIO(pio_addr=0x801fc000000)
+    uart = Uart8250(pio_addr=0x801fc0003f8)
+#    ethernet = NSGigE(configdata=NSGigEPciData(),
+#                      pci_bus=0, pci_dev=1, pci_func=0)
+#    etherint = NSGigEInt(device=Parent.ethernet)
+    console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
+#    bridge = PciFake(configdata=BridgePciData(), pci_bus=0, pci_dev=2, pci_func=0)
+
+#class FreeBSDTsunami(BaseTsunami):
+#    disk0 = FreeBSDRootDisk(delay='0us', driveID='master')
+#    ide = IdeController(disks=[Parent.disk0],
+#                        configdata=IdeControllerPciData(),
+#                        pci_func=0, pci_dev=0, pci_bus=0)
+
+#class LinuxTsunami(BaseTsunami):
+#    disk0 = LinuxRootDisk(delay='0us', driveID='master')
+#    ide = IdeController(disks=[Parent.disk0],
+#                        configdata=IdeControllerPciData(),
+#                        pci_func=0, pci_dev=0, pci_bus=0)
+
+class LinuxAlphaSystem(LinuxAlphaSystem):
+    magicbus = Bus()
+    physmem = PhysicalMemory(range = AddrRange('128MB'))
+    c1 = Connector(side_a=Parent.physmem, side_b=Parent.magicbus)
+    tsunami = BaseTsunami()
+    c2 = Connector(side_a=Parent.tsunami.cchip, side_a_name='pio', side_b=Parent.magicbus)
+    c3 = Connector(side_a=Parent.tsunami.pchip, side_a_name='pio', side_b=Parent.magicbus)
+    c4 = Connector(side_a=Parent.tsunami.pciconfig, side_a_name='pio', side_b=Parent.magicbus)
+    c5 = Connector(side_a=Parent.tsunami.fake_sm_chip, side_a_name='pio', side_b=Parent.magicbus)
+    c7 = Connector(side_a=Parent.tsunami.fake_uart1, side_a_name='pio', side_b=Parent.magicbus)
+    c8 = Connector(side_a=Parent.tsunami.fake_uart2, side_a_name='pio', side_b=Parent.magicbus)
+    c9 = Connector(side_a=Parent.tsunami.fake_uart3, side_a_name='pio', side_b=Parent.magicbus)
+    c10 = Connector(side_a=Parent.tsunami.fake_uart4, side_a_name='pio', side_b=Parent.magicbus)
+    c12 = Connector(side_a=Parent.tsunami.fake_ppc, side_a_name='pio', side_b=Parent.magicbus)
+    c14 = Connector(side_a=Parent.tsunami.fake_OROM, side_a_name='pio', side_b=Parent.magicbus)
+    c16 = Connector(side_a=Parent.tsunami.fake_pnp_addr, side_a_name='pio', side_b=Parent.magicbus)
+    c17 = Connector(side_a=Parent.tsunami.fake_pnp_write, side_a_name='pio', side_b=Parent.magicbus)
+    c18 = Connector(side_a=Parent.tsunami.fake_pnp_read0, side_a_name='pio', side_b=Parent.magicbus)
+    c19 = Connector(side_a=Parent.tsunami.fake_pnp_read1, side_a_name='pio', side_b=Parent.magicbus)
+    c20 = Connector(side_a=Parent.tsunami.fake_pnp_read2, side_a_name='pio', side_b=Parent.magicbus)
+    c21 = Connector(side_a=Parent.tsunami.fake_pnp_read3, side_a_name='pio', side_b=Parent.magicbus)
+    c22 = Connector(side_a=Parent.tsunami.fake_pnp_read4, side_a_name='pio', side_b=Parent.magicbus)
+    c23 = Connector(side_a=Parent.tsunami.fake_pnp_read5, side_a_name='pio', side_b=Parent.magicbus)
+    c24 = Connector(side_a=Parent.tsunami.fake_pnp_read6, side_a_name='pio', side_b=Parent.magicbus)
+    c25 = Connector(side_a=Parent.tsunami.fake_pnp_read7, side_a_name='pio', side_b=Parent.magicbus)
+    c27 = Connector(side_a=Parent.tsunami.fake_ata0, side_a_name='pio', side_b=Parent.magicbus)
+    c28 = Connector(side_a=Parent.tsunami.fake_ata1, side_a_name='pio', side_b=Parent.magicbus)
+    c30 = Connector(side_a=Parent.tsunami.fb, side_a_name='pio', side_b=Parent.magicbus)
+    c31 = Connector(side_a=Parent.tsunami.io, side_a_name='pio', side_b=Parent.magicbus)
+    c32 = Connector(side_a=Parent.tsunami.uart, side_a_name='pio', side_b=Parent.magicbus)
+    c33 = Connector(side_a=Parent.tsunami.console, side_a_name='pio', side_b=Parent.magicbus)
+    raw_image = RawDiskImage(image_file=disk('linux.img'),
+                             read_only=True)
+    simple_disk = SimpleDisk(disk=Parent.raw_image)
+    intrctrl = IntrControl()
+    cpu = SimpleCPU(mem=Parent.magicbus)
+    sim_console = SimConsole(listener=ConsoleListener(port=3456))
+    kernel = binary('vmlinux')
+    pal = binary('ts_osfpal')
+    console = binary('console')
+    boot_osflags = 'root=/dev/hda1 console=ttyS0'
+    readfile = os.path.join(test_base, 'halt.sh')
+
+
+BaseCPU.itb = AlphaITB()
+BaseCPU.dtb = AlphaDTB()
+BaseCPU.system = Parent.any
+
+class TsunamiRoot(Root):
+    pass
+
+
+root = TsunamiRoot(clock = '2GHz', system = LinuxAlphaSystem())
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index ca88b0701..6cef59796 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -507,6 +507,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
         data_read_pkt->req = data_read_req;
         data_read_pkt->data = new uint8_t[8];
 #endif
+        data_read_pkt->reset();
         data_read_pkt->addr = data_read_req->getPaddr();
         data_read_pkt->size = sizeof(T);
 
@@ -623,6 +624,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         data_write_pkt->data = new uint8_t[64];
         memcpy(data_write_pkt->data, &data, sizeof(T));
 #else
+        data_write_pkt->reset();
         data_write_pkt->data = (uint8_t *)&data;
 #endif
         data_write_pkt->addr = data_write_req->getPaddr();
@@ -990,6 +992,7 @@ SimpleCPU::tick()
             ifetch_pkt->req = ifetch_req;
             ifetch_pkt->size = sizeof(MachInst);
 #endif
+            ifetch_pkt->reset();
             ifetch_pkt->addr = ifetch_req->getPaddr();
 
             sendIcacheRequest(ifetch_pkt);
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index f68f132c8..fde8af6ae 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -72,12 +72,12 @@ AlphaConsole::AlphaConsole(Params *p)
     alphaAccess->inputChar = 0;
     bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
 
-    system->setAlphaAccess(pioAddr);
 }
 
 void
 AlphaConsole::startup()
 {
+    system->setAlphaAccess(pioAddr);
     alphaAccess->numCPUs = system->getNumCPUs();
     alphaAccess->kernStart = system->getKernelStart();
     alphaAccess->kernEnd = system->getKernelEnd();
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index b15f6fefb..81ad9a71d 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -74,7 +74,7 @@ TsunamiCChip::read(Packet &pkt)
     DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt.addr, pkt.size);
 
     assert(pkt.result == Unknown);
-    assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
+    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
 
     pkt.time = curTick + pioDelay;
     Addr regnum = (pkt.addr - pioAddr) >> 6;
@@ -179,8 +179,8 @@ TsunamiCChip::read(Packet &pkt)
       default:
         panic("invalid access size(?) for tsunami register!\n");
     }
-    DPRINTFN("Tsunami CChip: read  regnum=%#x size=%d data=%lld\n", regnum,
-            pkt.size, *data64);
+    DPRINTF(Tsunami, "Tsunami CChip: read  regnum=%#x size=%d data=%lld\n",
+            regnum, pkt.size, *data64);
 
     pkt.result = Success;
     return pioDelay;
@@ -282,7 +282,7 @@ TsunamiCChip::write(Packet &pkt)
             if(!supportedWrite)
                   panic("TSDEV_CC_MISC write not implemented\n");
 
-
+            break;
             case TSDEV_CC_AAR0:
             case TSDEV_CC_AAR1:
             case TSDEV_CC_AAR2:
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index 2f06cf493..66144b816 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -71,7 +71,7 @@ TsunamiPChip::read(Packet &pkt)
     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
 
     pkt.time = curTick + pioDelay;
-    Addr daddr = pkt.addr - pioAddr;
+    Addr daddr = (pkt.addr - pioAddr) >> 6;;
 
     uint64_t *data64;
 
@@ -159,7 +159,7 @@ TsunamiPChip::write(Packet &pkt)
 
     assert(pkt.result == Unknown);
     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
-    Addr daddr = pkt.addr - pioAddr;
+    Addr daddr = (pkt.addr - pioAddr) >> 6;
 
     uint64_t data64 = *(uint64_t *)pkt.data;
     assert(pkt.size == sizeof(uint64_t));
@@ -225,7 +225,7 @@ TsunamiPChip::write(Packet &pkt)
         case TSDEV_PC_PMONCNT:
               panic("PC_PMONCTN not implemented\n");
         default:
-            panic("Default in PChip Read reached reading 0x%x\n", daddr);
+            panic("Default in PChip write reached reading 0x%x\n", daddr);
 
     } // uint64_t
 
diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index 7c8899180..7e2f9d51f 100644
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -111,7 +111,7 @@ Tick
 Uart8250::read(Packet &pkt)
 {
     assert(pkt.result == Unknown);
-    assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
+    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
     assert(pkt.size == 1);
 
     pkt.time = curTick + pioDelay;
@@ -189,7 +189,10 @@ Uart8250::read(Packet &pkt)
             panic("Tried to access a UART port that doesn't exist\n");
             break;
     }
-
+/*    uint32_t d32 = *data;
+    DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
+*/
+    pkt.result = Success;
     return pioDelay;
 }
 
@@ -269,6 +272,7 @@ Uart8250::write(Packet &pkt)
             panic("Tried to access a UART port that doesn't exist\n");
             break;
     }
+    pkt.result = Success;
     return pioDelay;
 }
 
diff --git a/mem/bus.cc b/mem/bus.cc
index 8031dae96..5e84beb83 100644
--- a/mem/bus.cc
+++ b/mem/bus.cc
@@ -57,6 +57,7 @@ Bus::findPort(Addr addr, int id)
         if (portList[i].range == addr) {
             dest_id = portList[i].portId;
             found = true;
+            DPRINTF(Bus, "Found Addr: %llx on device %d\n", addr, dest_id);
         }
         i++;
     }
diff --git a/mem/packet.hh b/mem/packet.hh
index 91e56385d..843d34ac0 100644
--- a/mem/packet.hh
+++ b/mem/packet.hh
@@ -128,6 +128,12 @@ struct Packet
     /** Accessor function that returns the destination index of
         the packet. */
     short getDest() const { return dest; }
+
+    Packet()
+        : result(Unknown)
+        {}
+
+    void reset() { result = Unknown; }
 };
 
 #endif //__MEM_PACKET_HH
diff --git a/mem/vport.hh b/mem/vport.hh
index da036b981..fbc230ba3 100644
--- a/mem/vport.hh
+++ b/mem/vport.hh
@@ -63,39 +63,6 @@ class VirtualPort  : public FunctionalPort
      */
     bool nullExecContext() { return xc != NULL; }
 
-    /** Write a piece of data into a virtual address.
-     * @param vaddr virtual address to write to
-     * @param data data to write
-     */
-    template <typename T>
-    inline void write(Addr vaddr, T data)
-    {
-        Addr paddr;
-        if (xc)
-            paddr = TheISA::vtophys(xc,vaddr);
-        else
-            paddr = TheISA::vtophys(vaddr);
-
-        FunctionalPort::write(paddr, data);
-    }
-
-    /** Read data from a virtual address and return it.
-     * @param vaddr address to read
-     * @return data read
-     */
-
-    template <typename T>
-    inline T read(Addr vaddr)
-    {
-        Addr paddr;
-        if (xc)
-            paddr = TheISA::vtophys(xc,vaddr);
-        else
-            paddr = TheISA::vtophys(vaddr);
-
-        return FunctionalPort::read<T>(paddr);
-    }
-
     /** Version of readblob that translates virt->phys and deals
       * with page boundries. */
     virtual void readBlob(Addr addr, uint8_t *p, int size);