Registers: Add an ISA object which replaces the MiscRegFile.

This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.

46 files changed, 1068 insertions, 480 deletions

diff --git a/src/arch/SConscript b/src/arch/SConscript
index 0d801fcad..a67cf869a 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -46,6 +46,7 @@ isa_switch_hdrs = Split('''
         arguments.hh
         faults.hh
         interrupts.hh
+	isa.hh
         isa_traits.hh
         kernel_stats.hh
         locked_mem.hh
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 069db2551..b10885e01 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -37,6 +37,7 @@ if env['TARGET_ISA'] == 'alpha':
     Source('floatregfile.cc')
     Source('intregfile.cc')
     Source('ipr.cc')
+    Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
     Source('regfile.cc')
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
new file mode 100644
index 000000000..ed452cfc6
--- /dev/null
+++ b/src/arch/alpha/isa.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/alpha/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace AlphaISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+    miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string &section)
+{
+    miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
new file mode 100644
index 000000000..4c19659ab
--- /dev/null
+++ b/src/arch/alpha/isa.hh
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ALPHA_ISA_HH__
+#define __ARCH_ALPHA_ISA_HH__
+
+#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace AlphaISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+
+        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+        {
+            miscRegFile.expandForMultithreading(num_threads, num_vpes);
+        }
+
+        void reset(std::string core_name, ThreadID num_threads,
+                unsigned num_vpes, BaseCPU *_cpu)
+        {
+            miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+        }
+
+        int instAsid()
+        {
+            return miscRegFile.getInstAsid();
+        }
+
+        int dataAsid()
+        {
+            return miscRegFile.getDataAsid();
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int
+        flattenIntIndex(int reg)
+        {
+            return reg;
+        }
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index aea44976c..d2b37590a 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -55,6 +55,7 @@ output header {{
 output decoder {{
 #include <cmath>
 
+#include "arch/alpha/miscregfile.hh"
 #include "base/cprintf.hh"
 #include "base/fenv.hh"
 #include "base/loader/symtab.hh"
@@ -71,6 +72,7 @@ output exec {{
 #include "base/cp_annotate.hh"
 #include "sim/pseudo_inst.hh"
 #include "arch/alpha/ipr.hh"
+#include "arch/alpha/miscregfile.hh"
 #include "base/fenv.hh"
 #include "config/ss_compatible_fp.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index b3aa55b19..9009381b8 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -31,6 +31,7 @@
  */
 
 #include "arch/alpha/regfile.hh"
+#include "arch/alpha/miscregfile.hh"
 #include "cpu/thread_context.hh"
 
 using namespace std;
@@ -42,7 +43,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     floatRegFile.serialize(os);
-    miscRegFile.serialize(os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
@@ -55,7 +55,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     floatRegFile.unserialize(cp, section);
-    miscRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index cbd3657f7..59b76efd5 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -93,23 +93,10 @@ class RegFile {
   protected:
     IntRegFile intRegFile;          // (signed) integer register file
     FloatRegFile floatRegFile;      // floating point register file
-    MiscRegFile miscRegFile;        // control register file
 
   public:
 #if FULL_SYSTEM
     int intrflag;                   // interrupt flag
-
-    int
-    instAsid()
-    {
-        return miscRegFile.getInstAsid();
-    }
-
-    int
-    dataAsid()
-    {
-        return miscRegFile.getDataAsid();
-    }
 #endif // FULL_SYSTEM
 
     void
@@ -117,31 +104,6 @@ class RegFile {
     {
         intRegFile.clear();
         floatRegFile.clear();
-        miscRegFile.clear();
-    }
-
-    MiscReg
-    readMiscRegNoEffect(int miscReg)
-    {
-        return miscRegFile.readRegNoEffect(miscReg);
-    }
-
-    MiscReg
-    readMiscReg(int miscReg, ThreadContext *tc)
-    {
-        return miscRegFile.readReg(miscReg, tc);
-    }
-
-    void
-    setMiscRegNoEffect(int miscReg, const MiscReg &val)
-    {
-        miscRegFile.setRegNoEffect(miscReg, val);
-    }
-
-    void
-    setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
-    {
-        miscRegFile.setReg(miscReg, val, tc);
     }
 
     FloatReg
@@ -209,18 +171,6 @@ class RegFile {
         const std::string &section);
 };
 
-static inline int
-flattenIntIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
-static inline int
-flattenFloatIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 60a5ca3b0..a88a911f7 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -39,6 +39,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/mem.cc')
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
+    Source('isa.cc')
     Source('pagetable.cc')
     Source('regfile/regfile.cc')
     Source('tlb.cc')
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
new file mode 100644
index 000000000..944f19c0b
--- /dev/null
+++ b/src/arch/arm/isa.cc
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/arm/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace ArmISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect(miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg(miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect(miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg(miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+    //miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string &section)
+{
+    //miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
new file mode 100644
index 000000000..cb207bf13
--- /dev/null
+++ b/src/arch/arm/isa.hh
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ARM_ISA_HH__
+#define __ARCH_MRM_ISA_HH__
+
+#include "arch/arm/regfile/misc_regfile.hh"
+#include "arch/arm/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace ArmISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int
+        flattenIntIndex(int reg)
+        {
+            return reg;
+        }
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/regfile/misc_regfile.hh
index f7e5fbd98..eda0e8f05 100644
--- a/src/arch/arm/regfile/misc_regfile.hh
+++ b/src/arch/arm/regfile/misc_regfile.hh
@@ -31,6 +31,7 @@
 #ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 #define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 
+#include "arch/arm/isa_traits.hh"
 #include "arch/arm/types.hh"
 #include "sim/faults.hh"
 
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
index a4d6e9a4a..9821630e3 100644
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -59,11 +59,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
-    //SERIALZE_ARRAY(miscRegFile);
-    //SERIALIZE_SCALAR(miscRegs.fpcr);
-    //SERIALIZE_SCALAR(miscRegs.lock_flag);
-    //SERIALIZE_SCALAR(miscRegs.lock_addr);
-    //SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
 }
@@ -73,14 +68,8 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     //UNSERIALIZE_ARRAY(floatRegFile);
-    //UNSERIALZE_ARRAY(miscRegFile);
-    //UNSERIALIZE_SCALAR(miscRegs.fpcr);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
-    //UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
-
 }
 
 } // namespace ArmISA
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
index 5a812fecf..c432c0c28 100644
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -48,7 +48,6 @@ namespace ArmISA
       protected:
         IntRegFile intRegFile;		// (signed) integer register file
         FloatRegFile floatRegFile;	// floating point register file
-        MiscRegFile miscRegFile;	// control register file
 
       public:
 
@@ -56,28 +55,6 @@ namespace ArmISA
         {
             intRegFile.clear();
             floatRegFile.clear();
-            miscRegFile.clear();
-        }
-
-        MiscReg readMiscRegNoEffect(int miscReg)
-        {
-            return miscRegFile.readRegNoEffect(miscReg);
-        }
-
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc)
-        {
-            return miscRegFile.readReg(miscReg, tc);
-        }
-
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val)
-        {
-            miscRegFile.setRegNoEffect(miscReg, val);
-        }
-
-        void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc)
-        {
-            miscRegFile.setReg(miscReg, val, tc);
         }
 
         FloatRegVal readFloatReg(int floatReg)
@@ -171,22 +148,8 @@ namespace ArmISA
         void serialize(EventManager *em, std::ostream &os);
         void unserialize(EventManager *em, Checkpoint *cp,
                          const std::string &section);
-
-        void changeContext(RegContextParam param, RegContextVal val)
-        {
-        }
     };
 
-    static inline int flattenIntIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
-    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 0b470def6..a88829eae 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -34,6 +34,7 @@ Import('*')
 
 if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
+    Source('isa.cc')
     Source('regfile/int_regfile.cc')
     Source('regfile/float_regfile.cc')
     Source('regfile/misc_regfile.cc')
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
new file mode 100644
index 000000000..175374ca9
--- /dev/null
+++ b/src/arch/mips/isa.cc
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/mips/isa.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
+#include "cpu/thread_context.hh"
+
+namespace MipsISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect(miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg(miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect(miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg(miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+    //miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string &section)
+{
+    //miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
new file mode 100644
index 000000000..fd831834c
--- /dev/null
+++ b/src/arch/mips/isa.hh
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_MIPS_ISA_HH__
+#define __ARCH_MIPS_ISA_HH__
+
+#include "arch/mips/regfile/misc_regfile.hh"
+#include "arch/mips/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace MipsISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+
+        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+        {
+            miscRegFile.expandForMultithreading(num_threads, num_vpes);
+        }
+
+        void reset(std::string core_name, ThreadID num_threads,
+                unsigned num_vpes, BaseCPU *_cpu)
+        {
+            miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+        }
+
+        int instAsid()
+        {
+            return miscRegFile.getInstAsid();
+        }
+
+        int dataAsid()
+        {
+            return miscRegFile.getDataAsid();
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int
+        flattenIntIndex(int reg)
+        {
+            return reg;
+        }
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
index 908302866..4cc6725f7 100644
--- a/src/arch/mips/regfile.cc
+++ b/src/arch/mips/regfile.cc
@@ -193,11 +193,6 @@ RegFile::unserialize(Checkpoint *cp, const std::string &section)
 
 }
 
-static inline int flattenIntIndex(ThreadContext * tc, int reg)
-{
-    return reg;
-}
-
 void
 MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 {
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
index 975fad963..2b70ea9bd 100644
--- a/src/arch/mips/regfile/regfile.cc
+++ b/src/arch/mips/regfile/regfile.cc
@@ -42,7 +42,6 @@ RegFile::clear()
 {
     intRegFile.clear();
     floatRegFile.clear();
-    miscRegFile.clear();
 }
 
 void
@@ -51,7 +50,6 @@ RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
 {
     bzero(&intRegFile, sizeof(intRegFile));
     bzero(&floatRegFile, sizeof(floatRegFile));
-    miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
 }
 
 IntReg
@@ -66,31 +64,6 @@ RegFile::setIntReg(int intReg, const IntReg &val)
     return intRegFile.setReg(intReg, val);
 }
 
-MiscReg
-RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid)
-{
-    return miscRegFile.readRegNoEffect(miscReg, tid);
-}
-
-MiscReg
-RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid)
-{
-    return miscRegFile.readReg(miscReg, tc, tid);
-}
-
-void
-RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid)
-{
-    miscRegFile.setRegNoEffect(miscReg, val, tid);
-}
-
-void
-RegFile::setMiscReg(int miscReg, const MiscReg &val,
-                    ThreadContext *tc, ThreadID tid)
-{
-    miscRegFile.setReg(miscReg, val, tc, tid);
-}
-
 FloatRegVal
 RegFile::readFloatReg(int floatReg)
 {
@@ -144,17 +117,6 @@ RegFile::setShadowSet(int css){
     intRegFile.setShadowSet(css);
 }
 
-int
-RegFile::instAsid()
-{
-    return miscRegFile.getInstAsid();
-}
-
-int
-RegFile::dataAsid()
-{
-    return miscRegFile.getDataAsid();
-}
 
 Addr
 RegFile::readPC()
@@ -197,10 +159,6 @@ RegFile::serialize(EventManager *em, std::ostream &os)
 {
     intRegFile.serialize(os);
     //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
-    //SERIALZE_ARRAY(miscRegFile);
-    //SERIALIZE_SCALAR(miscRegs.fpcr);
-    //SERIALIZE_SCALAR(miscRegs.lock_flag);
-    //SERIALIZE_SCALAR(miscRegs.lock_addr);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
@@ -212,14 +170,9 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp,
 {
     intRegFile.unserialize(cp, section);
     //UNSERIALIZE_ARRAY(floatRegFile);
-    //UNSERIALZE_ARRAY(miscRegFile);
-    //UNSERIALIZE_SCALAR(miscRegs.fpcr);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
-    //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
-
 }
 
 } // namespace MipsISA
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 91951b078..b05f513b4 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -37,7 +37,6 @@
 //#include "arch/mips/mt.hh"
 #include "arch/mips/regfile/int_regfile.hh"
 #include "arch/mips/regfile/float_regfile.hh"
-#include "arch/mips/regfile/misc_regfile.hh"
 //#include "cpu/base.hh"
 #include "sim/faults.hh"
 
@@ -57,26 +56,16 @@ namespace MipsISA
 
         IntRegFile intRegFile;          // (signed) integer register file
         FloatRegFile floatRegFile;      // floating point register file
-        MiscRegFile miscRegFile;        // control register file
 
       public:
         void clear();
         void reset(std::string core_name, ThreadID num_threads,
                    unsigned num_vpes, BaseCPU *_cpu);
-        MiscRegFile *getMiscRegFilePtr();
 
         IntReg readIntReg(int intReg);
         Fault setIntReg(int intReg, const IntReg &val);
 
 
-        MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0);
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc,
-                            ThreadID tid = 0);
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val,
-                                ThreadID tid = 0);
-        void setMiscReg(int miscReg, const MiscReg &val,
-                        ThreadContext *tc, ThreadID tid = 0);
-
         FloatRegVal readFloatReg(int floatReg);
         FloatRegVal readFloatReg(int floatReg, int width);
         FloatRegBits readFloatRegBits(int floatReg);
@@ -89,9 +78,6 @@ namespace MipsISA
 
         void setShadowSet(int css);
 
-        int instAsid();
-        int dataAsid();
-
       public:
         Addr readPC();
         void setPC(Addr val);
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 1c77b6ff2..a88c77db9 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -98,17 +98,6 @@ namespace MipsISA {
     //
     //  Register File Utility Functions
     //
-    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
-    static inline int flattenIntIndex(ThreadContext * tc, int reg)
-    {
-        // Implement Shadow Sets Stuff Here;
-        return reg;
-    }
-
     static inline MachInst makeRegisterCopy(int dest, int src) {
         panic("makeRegisterCopy not implemented");
         return 0;
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 940cf2076..eb0d21598 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -36,6 +36,7 @@ if env['TARGET_ISA'] == 'sparc':
     Source('faults.cc')
     Source('floatregfile.cc')
     Source('intregfile.cc')
+    Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
     Source('regfile.cc')
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
new file mode 100644
index 000000000..3aeeb14ab
--- /dev/null
+++ b/src/arch/sparc/isa.cc
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/sparc/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace SparcISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+int
+ISA::flattenIntIndex(int reg)
+{
+    int gl = miscRegFile.readRegNoEffect(MISCREG_GL);
+    int cwp = miscRegFile.readRegNoEffect(MISCREG_CWP);
+    //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
+    int newReg;
+    //The total number of global registers
+    int numGlobals = (MaxGL + 1) * 8;
+    if(reg < 8)
+    {
+        //Global register
+        //Put it in the appropriate set of globals
+        newReg = reg + gl * 8;
+    }
+    else if(reg < NumIntArchRegs)
+    {
+        //Regular windowed register
+        //Put it in the window pointed to by cwp
+        newReg = numGlobals +
+            ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
+    }
+    else if(reg < NumIntArchRegs + NumMicroIntRegs)
+    {
+        //Microcode register
+        //Displace from the end of the regular registers
+        newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
+    }
+    else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
+    {
+        reg -= (NumIntArchRegs + NumMicroIntRegs);
+        if(reg < 8)
+        {
+            //Global register from the next window
+            //Put it in the appropriate set of globals
+            newReg = reg + gl * 8;
+        }
+        else
+        {
+            //Windowed register from the previous window
+            //Put it in the window before the one pointed to by cwp
+            newReg = numGlobals +
+                ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
+        }
+    }
+    else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
+    {
+        reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
+        if(reg < 8)
+        {
+            //Global register from the previous window
+            //Put it in the appropriate set of globals
+            newReg = reg + gl * 8;
+        }
+        else
+        {
+            //Windowed register from the next window
+            //Put it in the window after the one pointed to by cwp
+            newReg = numGlobals +
+                ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
+        }
+    }
+    else
+        panic("Tried to flatten invalid register index %d!\n", reg);
+    DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
+    return newReg;
+}
+
+void
+ISA::serialize(EventManager *em, std::ostream &os)
+{
+    miscRegFile.serialize(em, os);
+}
+
+void
+ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
+{
+    miscRegFile.unserialize(em, cp, section);
+}
+
+}
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
new file mode 100644
index 000000000..1dbfe7a28
--- /dev/null
+++ b/src/arch/sparc/isa.hh
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_ISA_HH__
+#define __ARCH_SPARC_ISA_HH__
+
+#include "arch/sparc/miscregfile.hh"
+#include "arch/sparc/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace SparcISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+
+        int instAsid()
+        {
+            return miscRegFile.getInstAsid();
+        }
+
+        int dataAsid()
+        {
+            return miscRegFile.getDataAsid();
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int flattenIntIndex(int reg);
+
+        int
+        flattenFloatIndex(int reg)
+        {
+            return reg;
+        }
+
+        void serialize(EventManager *em, std::ostream &os);
+        void unserialize(EventManager *em, Checkpoint *cp,
+                const std::string &section);
+
+        ISA()
+        {
+            clear();
+        }
+    };
+}
+
+#endif
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index a88c6c931..1daa43818 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -72,28 +72,6 @@ void RegFile::clear()
 {
     floatRegFile.clear();
     intRegFile.clear();
-    miscRegFile.clear();
-}
-
-MiscReg RegFile::readMiscRegNoEffect(int miscReg)
-{
-    return miscRegFile.readRegNoEffect(miscReg);
-}
-
-MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
-{
-    return miscRegFile.readReg(miscReg, tc);
-}
-
-void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
-{
-    miscRegFile.setRegNoEffect(miscReg, val);
-}
-
-void RegFile::setMiscReg(int miscReg, const MiscReg &val,
-        ThreadContext * tc)
-{
-    miscRegFile.setReg(miscReg, val, tc);
 }
 
 FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -151,80 +129,11 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
     intRegFile.setReg(intReg, val);
 }
 
-int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
-{
-    int gl = tc->readMiscRegNoEffect(MISCREG_GL);
-    int cwp = tc->readMiscRegNoEffect(MISCREG_CWP);
-    //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
-    int newReg;
-    //The total number of global registers
-    int numGlobals = (MaxGL + 1) * 8;
-    if(reg < 8)
-    {
-        //Global register
-        //Put it in the appropriate set of globals
-        newReg = reg + gl * 8;
-    }
-    else if(reg < NumIntArchRegs)
-    {
-        //Regular windowed register
-        //Put it in the window pointed to by cwp
-        newReg = numGlobals +
-            ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
-    }
-    else if(reg < NumIntArchRegs + NumMicroIntRegs)
-    {
-        //Microcode register
-        //Displace from the end of the regular registers
-        newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
-    }
-    else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
-    {
-        reg -= (NumIntArchRegs + NumMicroIntRegs);
-        if(reg < 8)
-        {
-            //Global register from the next window
-            //Put it in the appropriate set of globals
-            newReg = reg + gl * 8;
-        }
-        else
-        {
-            //Windowed register from the previous window
-            //Put it in the window before the one pointed to by cwp
-            newReg = numGlobals +
-                ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
-        }
-    }
-    else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
-    {
-        reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
-        if(reg < 8)
-        {
-            //Global register from the previous window
-            //Put it in the appropriate set of globals
-            newReg = reg + gl * 8;
-        }
-        else
-        {
-            //Windowed register from the next window
-            //Put it in the window after the one pointed to by cwp
-            newReg = numGlobals +
-                ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
-        }
-    }
-    else
-        panic("Tried to flatten invalid register index %d!\n", reg);
-    DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
-    return newReg;
-    //return intRegFile.flattenIndex(reg);
-}
-
 void
 RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     floatRegFile.serialize(os);
-    miscRegFile.serialize(em, os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
@@ -235,7 +144,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     floatRegFile.unserialize(cp, section);
-    miscRegFile.unserialize(em, cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 7da302eb7..2333d9da5 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -65,31 +65,11 @@ namespace SparcISA
       protected:
         IntRegFile intRegFile;          // integer register file
         FloatRegFile floatRegFile;      // floating point register file
-        MiscRegFile miscRegFile;        // control register file
 
       public:
 
         void clear();
 
-        MiscReg readMiscRegNoEffect(int miscReg);
-
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
-
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val);
-
-        void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc);
-
-        int instAsid()
-        {
-            return miscRegFile.getInstAsid();
-        }
-
-        int dataAsid()
-        {
-            return miscRegFile.getDataAsid();
-        }
-
         FloatReg readFloatReg(int floatReg, int width);
 
         FloatReg readFloatReg(int floatReg);
@@ -117,14 +97,6 @@ namespace SparcISA
       public:
     };
 
-    int flattenIntIndex(ThreadContext * tc, int reg);
-
-    static inline int
-    flattenFloatIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 4c0460e28..96967ea24 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -96,6 +96,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('insts/microregop.cc')
     Source('insts/static_inst.cc')
     Source('intregfile.cc')
+    Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
     Source('predecoder.cc')
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
new file mode 100644
index 000000000..4d8c8bb67
--- /dev/null
+++ b/src/arch/x86/isa.cc
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/isa.hh"
+#include "arch/x86/floatregs.hh"
+#include "cpu/thread_context.hh"
+
+namespace X86ISA
+{
+
+void
+ISA::clear()
+{
+    miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+int
+ISA::flattenIntIndex(int reg)
+{
+    //If we need to fold over the index to match byte semantics, do that.
+    //Otherwise, just strip off any extra bits and pass it through.
+    if (reg & (1 << 6))
+        return (reg & (~(1 << 6) - 0x4));
+    else
+        return (reg & ~(1 << 6));
+}
+
+int
+ISA::flattenFloatIndex(int reg)
+{
+    if (reg >= NUM_FLOATREGS) {
+        int top = miscRegFile.readRegNoEffect(MISCREG_X87_TOP);
+        reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
+    }
+    return reg;
+}
+
+void
+ISA::serialize(EventManager *em, std::ostream &os)
+{
+    miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
+{
+    miscRegFile.unserialize(cp, section);
+}
+
+}
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
new file mode 100644
index 000000000..34c803f0c
--- /dev/null
+++ b/src/arch/x86/isa.hh
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_ISA_HH__
+#define __ARCH_X86_ISA_HH__
+
+#include "arch/x86/miscregfile.hh"
+#include "arch/x86/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace X86ISA
+{
+    class ISA
+    {
+      protected:
+        MiscRegFile miscRegFile;
+
+      public:
+        int instAsid()
+        {
+            //XXX This doesn't make sense in x86
+            return 0;
+        }
+
+        int dataAsid()
+        {
+            //XXX This doesn't make sense in x86
+            return 0;
+        }
+
+        void clear();
+
+        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+        void setMiscRegNoEffect(int miscReg, const MiscReg val);
+        void setMiscReg(int miscReg, const MiscReg val,
+                ThreadContext *tc);
+
+        int flattenIntIndex(int reg);
+        int flattenFloatIndex(int reg);
+
+        void serialize(EventManager *em, std::ostream &os);
+        void unserialize(EventManager *em, Checkpoint *cp,
+                const std::string &section);
+    };
+}
+
+#endif
diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index 74dcbcbea..f2329b7b4 100644
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -99,14 +99,10 @@ class Checkpoint;
 
 namespace X86ISA
 {
-    //These will have to be updated in the future.
-    const int NumMiscArchRegs = NUM_MISCREGS;
-    const int NumMiscRegs = NUM_MISCREGS;
-
     class MiscRegFile
     {
       protected:
-        MiscReg regVal[NumMiscRegs];
+        MiscReg regVal[NUM_MISCREGS];
         void updateHandyM5Reg(Efer efer, CR0 cr0,
                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
 
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index c643a7924..54c7c9121 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -87,6 +87,7 @@
  */
 
 #include "arch/x86/isa_traits.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/process.hh"
 #include "arch/x86/segmentregs.hh"
 #include "arch/x86/types.hh"
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 83279902e..f6a9c1480 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -86,6 +86,7 @@
  */
 
 #include "arch/x86/floatregs.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/regfile.hh"
 #include "base/trace.hh"
 #include "sim/serialize.hh"
@@ -130,28 +131,6 @@ void RegFile::clear()
 {
     floatRegFile.clear();
     intRegFile.clear();
-    miscRegFile.clear();
-}
-
-MiscReg RegFile::readMiscRegNoEffect(int miscReg)
-{
-    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
-}
-
-MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
-{
-    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
-}
-
-void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
-{
-    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
-}
-
-void RegFile::setMiscReg(int miscReg, const MiscReg &val,
-        ThreadContext * tc)
-{
-    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
 }
 
 FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -209,50 +188,11 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
     intRegFile.setReg(intReg, val);
 }
 
-int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
-{
-    //If we need to fold over the index to match byte semantics, do that.
-    //Otherwise, just strip off any extra bits and pass it through.
-    if (reg & (1 << 6))
-        return (reg & (~(1 << 6) - 0x4));
-    else
-        return (reg & ~(1 << 6));
-}
-
-int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg)
-{
-    if (reg >= NUM_FLOATREGS) {
-        int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP);
-        reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
-    }
-    return reg;
-}
-
-void
-RegFile::serialize(EventManager *em, std::ostream &os)
-{
-    intRegFile.serialize(os);
-    floatRegFile.serialize(os);
-    miscRegFile.serialize(os);
-    SERIALIZE_SCALAR(rip);
-    SERIALIZE_SCALAR(nextRip);
-}
-
 void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
-{
-    intRegFile.unserialize(cp, section);
-    floatRegFile.unserialize(cp, section);
-    miscRegFile.unserialize(cp, section);
-    UNSERIALIZE_SCALAR(rip);
-    UNSERIALIZE_SCALAR(nextRip);
-}
-
-void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
-    //panic("copyMiscRegs not implemented for x86!\n");
     warn("copyMiscRegs is naively implemented for x86\n");
-    for (int i = 0; i < X86ISA::NumMiscRegs; ++i) {
+    for (int i = 0; i < NUM_MISCREGS; ++i) {
         if ( ( i != MISCREG_CR1 &&
              !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
              !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
@@ -260,10 +200,10 @@ void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
         }
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
     }
-
 }
 
-void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
+void
+X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 {
     panic("copyRegs not implemented for x86!\n");
     //copy int regs
@@ -273,3 +213,17 @@ void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
     dest->setPC(src->readPC());
     dest->setNextPC(src->readNextPC());
 }
+
+void
+RegFile::serialize(EventManager *em, std::ostream &os)
+{
+    intRegFile.serialize(os);
+    floatRegFile.serialize(os);
+}
+
+void
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
+{
+    intRegFile.unserialize(cp, section);
+    floatRegFile.unserialize(cp, section);
+}
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index 4f285254a..0414622a2 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -62,8 +62,8 @@
 
 #include "arch/x86/floatregfile.hh"
 #include "arch/x86/intregfile.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/isa_traits.hh"
-#include "arch/x86/miscregfile.hh"
 #include "arch/x86/types.hh"
 #include "base/types.hh"
 
@@ -72,6 +72,9 @@ class EventManager;
 
 namespace X86ISA
 {
+    const int NumMiscArchRegs = NUM_MISCREGS;
+    const int NumMiscRegs = NUM_MISCREGS;
+
     class RegFile
     {
       protected:
@@ -91,33 +94,11 @@ namespace X86ISA
       protected:
         IntRegFile intRegFile; // integer register file
         FloatRegFile floatRegFile; // floating point register file
-        MiscRegFile miscRegFile; // control register file
 
       public:
 
         void clear();
 
-        MiscReg readMiscRegNoEffect(int miscReg);
-
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
-
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val);
-
-        void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc);
-
-        int instAsid()
-        {
-            //XXX This doesn't make sense in x86
-            return 0;
-        }
-
-        int dataAsid()
-        {
-            //XXX This doesn't make sense in x86
-            return 0;
-        }
-
         FloatReg readFloatReg(int floatReg, int width);
 
         FloatReg readFloatReg(int floatReg);
@@ -141,14 +122,8 @@ namespace X86ISA
         void serialize(EventManager *em, std::ostream &os);
         void unserialize(EventManager *em, Checkpoint *cp,
             const std::string &section);
-
-      public:
     };
 
-    int flattenIntIndex(ThreadContext * tc, int reg);
-
-    int flattenFloatIndex(ThreadContext * tc, int reg);
-
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 1478c3e66..c67c193ea 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -60,6 +60,7 @@
 #include "config/full_system.hh"
 
 #include "arch/x86/insts/microldstop.hh"
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/pagetable.hh"
 #include "arch/x86/tlb.hh"
 #include "arch/x86/x86_traits.hh"
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 9290dc024..dbb2bc361 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -58,6 +58,7 @@
 #ifndef __ARCH_X86_UTILITY_HH__
 #define __ARCH_X86_UTILITY_HH__
 
+#include "arch/x86/miscregs.hh"
 #include "arch/x86/types.hh"
 #include "base/hashmap.hh"
 #include "base/misc.hh"
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 3d7d713e8..51d62e179 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -168,7 +168,6 @@ InOrderCPU::InOrderCPU(Params *params)
       coreType("default"),
       _status(Idle),
       tickEvent(this),
-      miscRegFile(this),
       timeBuffer(2 , 2),
       removeInstsThisCycle(false),
       activityRec(params->name, NumStages, 10, params->activity),
@@ -267,15 +266,11 @@ InOrderCPU::InOrderCPU(Params *params)
 
         intRegFile[tid].clear();
         floatRegFile[tid].clear();
-    }
+        isa[tid].clear();
 
-    // Update miscRegFile if necessary
-    if (numThreads > 1) {
-        miscRegFile.expandForMultithreading(numThreads, numVirtProcs);
+        isa[tid].expandForMultithreading(numThreads, numVirtProcs);
     }
 
-    miscRegFile.clear();
-
     lastRunningCycle = curTick;
     contextSwitch = false;
 
@@ -461,7 +456,10 @@ InOrderCPU::readFunctional(Addr addr, uint32_t &buffer)
 void
 InOrderCPU::reset()
 {
-  miscRegFile.reset(coreType, numThreads, numVirtProcs, dynamic_cast<BaseCPU*>(this));
+    for (int i = 0; i < numThreads; i++) {
+        isa[i].reset(coreType, numThreads,
+                numVirtProcs, dynamic_cast<BaseCPU*>(this));
+    }
 }
 
 Port*
@@ -966,25 +964,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
 MiscReg
 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    return miscRegFile.readRegNoEffect(misc_reg, tid);
+    return isa[tid].readMiscRegNoEffect(misc_reg);
 }
 
 MiscReg
 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
 {
-    return miscRegFile.readReg(misc_reg, tcBase(tid), tid);
+    return isa[tid].readMiscReg(misc_reg, tcBase(tid));
 }
 
 void
 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    miscRegFile.setRegNoEffect(misc_reg, val, tid);
+    isa[tid].setMiscRegNoEffect(misc_reg, val);
 }
 
 void
 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    miscRegFile.setReg(misc_reg, val, tcBase(tid), tid);
+    isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 794d81def..bfc5139cf 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -39,6 +39,7 @@
 #include <vector>
 
 #include "arch/isa_traits.hh"
+#include "arch/types.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "base/types.hh"
@@ -76,8 +77,8 @@ class InOrderCPU : public BaseCPU
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscReg MiscReg;
     typedef TheISA::RegFile RegFile;
+    typedef TheISA::MiscReg MiscReg;
 
     //DynInstPtr TypeDefs
     typedef ThePipeline::DynInstPtr DynInstPtr;
@@ -259,7 +260,9 @@ class InOrderCPU : public BaseCPU
     /** The Register File for the CPU */
     TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
     TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
-    TheISA::MiscRegFile miscRegFile;
+
+    /** ISA state */
+    TheISA::ISA isa[ThePipeline::MaxThreads];
 
     /** Dependency Tracker for Integer & Floating Point Regs */
     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index f3cf3ec44..aac8901b3 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -211,6 +211,12 @@ class InOrderThreadContext : public ThreadContext
      * write might have as defined by the architecture. */
     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 
+    virtual int flattenIntIndex(int reg)
+    { return cpu->isa[thread->readTid()].flattenIntIndex(reg); }
+
+    virtual int flattenFloatIndex(int reg)
+    { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); }
+
     virtual void activateContext(int delay)
     { cpu->activateContext(thread->readTid(), delay); }
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 621b6c1b9..2f8869b6f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1180,14 +1180,14 @@ template <class Impl>
 TheISA::MiscReg
 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
+    return this->isa[tid].readMiscRegNoEffect(misc_reg);
 }
 
 template <class Impl>
 TheISA::MiscReg
 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
 }
 
 template <class Impl>
@@ -1195,7 +1195,7 @@ void
 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
         const TheISA::MiscReg &val, ThreadID tid)
 {
-    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
+    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
 }
 
 template <class Impl>
@@ -1203,7 +1203,7 @@ void
 FullO3CPU<Impl>::setMiscReg(int misc_reg,
         const TheISA::MiscReg &val, ThreadID tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 5cf27df75..1289785dc 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -395,11 +395,11 @@ class FullO3CPU : public BaseO3CPU
 
     /** Get instruction asid. */
     int getInstAsid(ThreadID tid)
-    { return regFile.miscRegs[tid].getInstAsid(); }
+    { return isa[tid].instAsid(); }
 
     /** Get data asid. */
     int getDataAsid(ThreadID tid)
-    { return regFile.miscRegs[tid].getDataAsid(); }
+    { return isa[tid].dataAsid(); }
 #else
     /** Get instruction asid. */
     int getInstAsid(ThreadID tid)
@@ -603,6 +603,8 @@ class FullO3CPU : public BaseO3CPU
     /** Integer Register Scoreboard */
     Scoreboard scoreboard;
 
+    TheISA::ISA isa[Impl::MaxThreads];
+
   public:
     /** Enum to give each stage a specific index, so when calling
      *  activateStage() or deactivateStage(), they can specify which stage
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 07f8d487b..e7b20e4a9 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -57,8 +57,6 @@ class PhysRegFile
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscRegFile MiscRegFile;
-    typedef TheISA::MiscReg MiscReg;
 
     typedef union {
         FloatReg d;
@@ -230,30 +228,6 @@ class PhysRegFile
         floatRegFile[reg_idx].q = val;
     }
 
-    MiscReg
-    readMiscRegNoEffect(int misc_reg, ThreadID tid)
-    {
-        return miscRegs[tid].readRegNoEffect(misc_reg);
-    }
-
-    MiscReg
-    readMiscReg(int misc_reg, ThreadID tid)
-    {
-        return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid));
-    }
-
-    void
-    setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
-    {
-        miscRegs[tid].setRegNoEffect(misc_reg, val);
-    }
-
-    void
-    setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
-    {
-        miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid));
-    }
-
   public:
     /** (signed) integer register file. */
     IntReg *intRegFile;
@@ -261,9 +235,6 @@ class PhysRegFile
     /** Floating point register file. */
     PhysFloatReg *floatRegFile;
 
-    /** Miscellaneous register file. */
-    MiscRegFile miscRegs[Impl::MaxThreads];
-
 #if FULL_SYSTEM
   private:
     int intrflag;                       // interrupt flag
@@ -289,10 +260,6 @@ PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
     intRegFile = new IntReg[numPhysicalIntRegs];
     floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
 
-    for (int i = 0; i < Impl::MaxThreads; ++i) {
-        miscRegs[i].clear();
-    }
-
     memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
     memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
 }
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 2bca6f81c..dd480f81c 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -959,11 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
         RegIndex src_reg = inst->srcRegIdx(src_idx);
         RegIndex flat_src_reg = src_reg;
         if (src_reg < TheISA::FP_Base_DepTag) {
-            flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
+            flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
         } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
             src_reg = src_reg - TheISA::FP_Base_DepTag;
-            flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg);
+            flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
             flat_src_reg += TheISA::NumIntRegs;
         } else {
             flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
@@ -1009,7 +1009,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
         RegIndex flat_dest_reg = dest_reg;
         if (dest_reg < TheISA::FP_Base_DepTag) {
             // Integer registers are flattened.
-            flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
+            flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
         } else {
             // Floating point and Miscellaneous registers need their indexes
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index b10305d5d..a3f1ce58f 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -226,6 +226,9 @@ class O3ThreadContext : public ThreadContext
      * write might have as defined by the architecture. */
     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 
+    virtual int flattenIntIndex(int reg);
+    virtual int flattenFloatIndex(int reg);
+
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
     virtual unsigned readStCondFailures()
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index bce334dc4..6527f5d06 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -272,7 +272,7 @@ template <class Impl>
 uint64_t
 O3ThreadContext<Impl>::readIntReg(int reg_idx)
 {
-    reg_idx = TheISA::flattenIntIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
     return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
@@ -280,7 +280,7 @@ template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     switch(width) {
       case 32:
         return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
@@ -296,7 +296,7 @@ template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
 }
 
@@ -305,7 +305,7 @@ TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
 {
     DPRINTF(Fault, "Reading floatint register through the TC!\n");
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
@@ -313,7 +313,7 @@ template <class Impl>
 TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
@@ -321,7 +321,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
 {
-    reg_idx = TheISA::flattenIntIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
     cpu->setArchIntReg(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
@@ -334,7 +334,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     switch(width) {
       case 32:
         cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
@@ -354,7 +354,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
 
     if (!thread->trapPending && !thread->inSyscall) {
@@ -368,7 +368,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
                                              int width)
 {
     DPRINTF(Fault, "Setting floatint register through the TC!\n");
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
@@ -381,7 +381,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
@@ -439,6 +439,20 @@ O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
 }
 
 template <class Impl>
+int
+O3ThreadContext<Impl>::flattenIntIndex(int reg)
+{
+    return cpu->isa[thread->threadId()].flattenIntIndex(reg);
+}
+
+template <class Impl>
+int
+O3ThreadContext<Impl>::flattenFloatIndex(int reg)
+{
+    return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
+}
+
+template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 {
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 08dd45640..3199263be 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -32,6 +32,7 @@
 #ifndef __CPU_SIMPLE_THREAD_HH__
 #define __CPU_SIMPLE_THREAD_HH__
 
+#include "arch/isa.hh"
 #include "arch/isa_traits.hh"
 #include "arch/regfile.hh"
 #include "arch/tlb.hh"
@@ -90,7 +91,6 @@ class SimpleThread : public ThreadState
   protected:
     typedef TheISA::RegFile RegFile;
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::MiscRegFile MiscRegFile;
     typedef TheISA::MiscReg MiscReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
@@ -99,6 +99,7 @@ class SimpleThread : public ThreadState
 
   protected:
     RegFile regs;       // correct-path register context
+    TheISA::ISA isa;    // one "instance" of the current ISA.
 
   public:
     // pointer to CPU associated with this SimpleThread
@@ -164,8 +165,8 @@ class SimpleThread : public ThreadState
     }
 
 #if FULL_SYSTEM
-    int getInstAsid() { return regs.instAsid(); }
-    int getDataAsid() { return regs.dataAsid(); }
+    int getInstAsid() { return isa.instAsid(); }
+    int getDataAsid() { return isa.dataAsid(); }
 
     void dumpFuncProfile();
 
@@ -229,61 +230,61 @@ class SimpleThread : public ThreadState
     //
     uint64_t readIntReg(int reg_idx)
     {
-        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenIntIndex(reg_idx);
         return regs.readIntReg(flatIndex);
     }
 
     FloatReg readFloatReg(int reg_idx, int width)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatReg(flatIndex, width);
     }
 
     FloatReg readFloatReg(int reg_idx)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatReg(flatIndex);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx, int width)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatRegBits(flatIndex, width);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatRegBits(flatIndex);
     }
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenIntIndex(reg_idx);
         regs.setIntReg(flatIndex, val);
     }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatReg(flatIndex, val, width);
     }
 
     void setFloatReg(int reg_idx, FloatReg val)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatReg(flatIndex, val);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatRegBits(flatIndex, val, width);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatRegBits(flatIndex, val);
     }
 
@@ -340,25 +341,37 @@ class SimpleThread : public ThreadState
     MiscReg
     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
     {
-        return regs.readMiscRegNoEffect(misc_reg);
+        return isa.readMiscRegNoEffect(misc_reg);
     }
 
     MiscReg
     readMiscReg(int misc_reg, ThreadID tid = 0)
     {
-        return regs.readMiscReg(misc_reg, tc);
+        return isa.readMiscReg(misc_reg, tc);
     }
 
     void
     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
     {
-        return regs.setMiscRegNoEffect(misc_reg, val);
+        return isa.setMiscRegNoEffect(misc_reg, val);
     }
 
     void
     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
     {
-        return regs.setMiscReg(misc_reg, val, tc);
+        return isa.setMiscReg(misc_reg, val, tc);
+    }
+
+    int
+    flattenIntIndex(int reg)
+    {
+        return isa.flattenIntIndex(reg);
+    }
+
+    int
+    flattenFloatIndex(int reg)
+    {
+        return isa.flattenFloatIndex(reg);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 3e37572d8..8963553d5 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -84,7 +84,6 @@ class ThreadContext
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscRegFile MiscRegFile;
     typedef TheISA::MiscReg MiscReg;
   public:
 
@@ -234,6 +233,9 @@ class ThreadContext
 
     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
+    virtual int flattenIntIndex(int reg) = 0;
+    virtual int flattenFloatIndex(int reg) = 0;
+
     virtual uint64_t
     readRegOtherThread(int misc_reg, ThreadID tid)
     {
@@ -434,6 +436,12 @@ class ProxyThreadContext : public ThreadContext
     void setMiscReg(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
+    int flattenIntIndex(int reg)
+    { return actualTC->flattenIntIndex(reg); }
+
+    int flattenFloatIndex(int reg)
+    { return actualTC->flattenFloatIndex(reg); }
+
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }
 
diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index 2234f55fe..8624b44da 100644
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -55,6 +55,7 @@ class Tru64 {};
 #include <string.h>     // for memset()
 #include <unistd.h>
 
+#include "arch/alpha/miscregfile.hh"
 #include "cpu/base.hh"
 #include "sim/core.hh"
 #include "sim/syscall_emul.hh"