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authorNilay Vaish <nilay@cs.wisc.edu>2012-03-01 11:37:03 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-03-01 11:37:03 -0600
commit4b32c9fb4d9d1b1507a4f0683b131d70918831ce (patch)
tree0b0f670e2d8445b10e8772dd8173902e880c756b
parentc80af04d7df7586352841a65a4398baf21e0c122 (diff)
downloadgem5-4b32c9fb4d9d1b1507a4f0683b131d70918831ce.tar.xz
x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the walker port. This port is required for correctly connecting the walker ports for the cpu just switched in
-rw-r--r--src/arch/x86/pagetable_walker.hh2
-rw-r--r--src/arch/x86/tlb.cc6
-rw-r--r--src/arch/x86/tlb.hh2
3 files changed, 9 insertions, 1 deletions
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index d433c7b98..90f075280 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -80,7 +80,6 @@ namespace X86ISA
friend class WalkerPort;
WalkerPort port;
- Port *getPort(const std::string &if_name, int idx = -1);
// State to track each walk of the page table
class WalkerState : public FastAlloc
@@ -167,6 +166,7 @@ namespace X86ISA
RequestPtr req, BaseTLB::Mode mode);
Fault startFunctional(ThreadContext * _tc, Addr &addr,
Addr &pageSize, BaseTLB::Mode mode);
+ Port *getPort(const std::string &if_name, int idx = -1);
protected:
// The TLB we're supposed to load.
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ff65eb04c..456f03208 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -421,6 +421,12 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
{
}
+Port *
+TLB::getPort()
+{
+ return walker->getPort("port");
+}
+
} // namespace X86ISA
X86ISA::TLB *
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 449ca19ce..a943683af 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -120,6 +120,8 @@ namespace X86ISA
// Checkpointing
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+ virtual Port * getPort();
};
}