Put regression tests back into m5. They are located in the "tests" directory. The directory output and reference outputs have changed slightly. Now the directory is ALPHA_SE/test/<test>/<cpu_model>/, and for the reference stats <test>/ref/<arch>/<cpu_model>

Right now only non-SMT SE regression tests have been added back in.  The rest are pending getting SMT working, and consolidating the FS configuration files.

Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.

Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work.  The test itself should probably work once the code is fixed.

SConstruct:
    Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again.
src/cpu/SConscript:
    Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only.

--HG--
extra : convert_revision : 34e6286150aae8f316ae694f6c00be8f510522f2

19 files changed, 3483 insertions, 4 deletions

diff --git a/SConstruct b/SConstruct
index b18fe66d3..259b6c583 100644
--- a/SConstruct
+++ b/SConstruct
@@ -494,10 +494,10 @@ for build_path in build_paths:
                          exports = 'env')
 
     # Set up the regression tests for each build.
-#    for e in envList:
-#        SConscript('m5-test/SConscript',
-#                   build_dir = os.path.join(build_dir, 'test', e.Label),
-#                   exports = { 'env' : e }, duplicate = False)
+    for e in envList:
+        SConscript('tests/SConscript',
+                   build_dir = os.path.join(build_path, 'test', e.Label),
+                   exports = { 'env' : e }, duplicate = False)
 
 Help(help_text)
 
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 442c190ce..7d45c7870 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -114,6 +114,9 @@ CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
 #
 #################################################################
 
+# Keep a list of CPU models that support SMT
+env['SMT_CPU_MODELS'] = []
+
 sources = []
 
 need_simple_base = False
@@ -157,6 +160,7 @@ if 'O3CPU' in env['CPU_MODELS']:
         ''')
     if env['USE_CHECKER']:
         sources += Split('o3/checker_builder.cc')
+    env['SMT_CPU_MODELS'].append('O3CPU')
 
 if 'OzoneCPU' in env['CPU_MODELS']:
     need_bp_unit = True
diff --git a/tests/SConscript b/tests/SConscript
new file mode 100644
index 000000000..5eadce6d4
--- /dev/null
+++ b/tests/SConscript
@@ -0,0 +1,244 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import sys
+import glob
+from SCons.Script.SConscript import SConsEnvironment
+
+Import('env')
+
+env['DIFFOUT'] = File('diff-out')
+
+# Dict that accumulates lists of tests by category (quick, medium, long)
+env.Tests = {}
+
+def contents(node):
+    return file(str(node)).read()
+
+def check_test(target, source, env):
+    """Check output from running test.
+
+    Targets are as follows:
+    target[0] : outdiff
+    target[1] : statsdiff
+    target[2] : status
+
+    """
+    # make sure target files are all gone
+    for t in target:
+        if os.path.exists(t.abspath):
+            Execute(Delete(t.abspath))
+    # Run diff on output & ref directories to find differences.
+    # Exclude m5stats.txt since we will use diff-out on that.
+    Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' +
+                      '-I "^command line:" ' +		# for stdout file
+                      '-I "^M5 compiled on" ' +		# for stderr file
+                      '-I "^M5 simulation started" ' +	# for stderr file
+                      '-I "^Simulation complete at" ' +	# for stderr file
+                      '-I "^Listening for" ' +		# for stderr file
+                      '--exclude=m5stats.txt --exclude=SCCS ' +
+                      '--exclude=${TARGETS[0].file} ' +
+                      '> ${TARGETS[0]}', target=target, source=source), None)
+    print "===== Output differences ====="
+    print contents(target[0])
+    # Run diff-out on m5stats.txt file
+    status = Execute(env.subst('$DIFFOUT $SOURCES > ${TARGETS[1]}',
+                               target=target, source=source),
+                     strfunction=None)
+    print "===== Statistics differences ====="
+    print contents(target[1])
+    # Generate status file contents based on exit status of diff-out
+    if status == 0:
+        status_str = "passed."
+    else:
+        status_str = "FAILED!"
+    f = file(str(target[2]), 'w')
+    print >>f, env.subst('${TARGETS[2].dir}', target=target, source=source), \
+          status_str
+    f.close()
+    # done
+    return 0
+
+def check_test_string(target, source, env):
+    return env.subst("Comparing outputs in ${TARGETS[0].dir}.",
+                     target=target, source=source)
+
+testAction = env.Action(check_test, check_test_string)
+
+def print_test(target, source, env):
+    print '***** ' + contents(source[0])
+    return 0
+
+printAction = env.Action(print_test, strfunction = None)
+
+def update_test(target, source, env):
+    """Update reference test outputs.
+
+    Target is phony.  First two sources are the ref & new m5stats.txt
+    files, respectively.  We actually copy everything in the
+    respective directories except the status & diff output files.
+
+    """
+    dest_dir = str(source[0].get_dir())
+    src_dir = str(source[1].get_dir())
+    dest_files = os.listdir(dest_dir)
+    src_files = os.listdir(src_dir)
+    # Exclude status & diff outputs
+    for f in ('outdiff', 'statsdiff', 'status'):
+        if f in src_files:
+            src_files.remove(f)
+    for f in src_files:
+        if f in dest_files:
+            print "  Replacing file", f
+            dest_files.remove(f)
+        else:
+            print "  Creating new file", f
+        copyAction = Copy(os.path.join(dest_dir, f), os.path.join(src_dir, f))
+        copyAction.strfunction = None
+        Execute(copyAction)
+    # warn about any files in dest not overwritten (other than SCCS dir)
+    if 'SCCS' in dest_files:
+        dest_files.remove('SCCS')
+    if dest_files:
+        print "Warning: file(s) in", dest_dir, "not updated:",
+        print ', '.join(dest_files)
+    return 0
+
+def update_test_string(target, source, env):
+    return env.subst("Updating ${SOURCES[0].dir} from ${SOURCES[1].dir}",
+                     target=target, source=source)
+
+updateAction = env.Action(update_test, update_test_string)
+
+def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=15):
+    """Define a test.
+
+    Args:
+    category -- string describing test category (e.g., 'quick')
+    cpu_list -- list of CPUs to runs this test on (blank means all compiled CPUs)
+    os_list -- list of OSs to run this test on
+    refdir -- subdirectory containing reference output (default 'ref')
+    timeout -- test timeout in minutes (only enforced on pool)
+
+    """
+
+    default_refdir = False
+    if refdir == 'ref':
+        default_refdir = True
+    if len(cpu_list) == 0:
+        cpu_list = env['CPU_MODELS']
+#    if len(os_list) == 0:
+#        raise RuntimeError, "No OS specified"
+#    else:
+#        for test_os in os_list:
+#            build_cpu_test(env, category, test_os, cpu_list, refdir, timeout)
+    # Loop through CPU models and generate proper options, ref directories for each
+    for cpu in cpu_list:
+        test_os = ''
+        if cpu == "AtomicSimpleCPU":
+            cpu_option = ('','atomic/')
+        elif cpu == "TimingSimpleCPU":
+            cpu_option = ('--timing','timing/')
+        elif cpu == "O3CPU":
+            cpu_option = ('--detailed','detailed/')
+        else:
+            raise TypeError, "Unknown CPU model specified"
+
+        if default_refdir:
+            # Reference stats located in ref/arch/os/cpu or ref/arch/cpu if no OS specified
+            test_refdir = os.path.join(refdir, env['TARGET_ISA'])
+            if test_os != '':
+                test_refdir = os.path.join(test_refdir, test_os)
+            cpu_refdir = os.path.join(test_refdir, cpu_option[1])
+
+        ref_stats = os.path.join(cpu_refdir, 'm5stats.txt')
+
+        # base command for running test
+        base_cmd = '${SOURCES[0]} -d $TARGET.dir ${SOURCES[1]}'
+        base_cmd = base_cmd + ' ' + cpu_option[0]
+        # stdout and stderr files
+        cmd_stdout = '${TARGETS[0]}'
+        cmd_stderr = '${TARGETS[1]}'
+
+        stdout_string = cpu_option[1] + 'stdout'
+        stderr_string = cpu_option[1] + 'stderr'
+        m5stats_string = cpu_option[1] + 'm5stats.txt'
+        outdiff_string =  cpu_option[1] + 'outdiff'
+        statsdiff_string = cpu_option[1] + 'statsdiff'
+        status_string = cpu_option[1] + 'status'
+
+        # Prefix test run with batch job submission command if appropriate.
+        # Output redirection is also different for batch runs.
+        # Batch command also supports timeout arg (in seconds, not minutes).
+        if env['BATCH']:
+            cmd = [env['BATCH_CMD'], '-t', str(timeout * 60),
+                   '-o', cmd_stdout, '-e', cmd_stderr, base_cmd]
+        else:
+            cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr]
+            
+        env.Command([stdout_string, stderr_string, m5stats_string], [env.M5Binary, 'run.py'],
+                    ' '.join(cmd))
+
+        # order of targets is important... see check_test
+        env.Command([outdiff_string, statsdiff_string, status_string],
+                    [ref_stats, m5stats_string],
+                    testAction)
+
+        # phony target to echo status
+        if env['update_ref']:
+            p = env.Command(cpu_option[1] + '_update', [ref_stats, m5stats_string, status_string],
+                            updateAction)
+        else:
+            p = env.Command(cpu_option[1] + '_print', [status_string], printAction)
+        env.AlwaysBuild(p)
+
+        env.Tests.setdefault(category, [])
+        env.Tests[category] += p
+
+# Make test_builder a "wrapper" function.  See SCons wiki page at
+# http://www.scons.org/cgi-bin/wiki/WrapperFunctions.
+SConsEnvironment.Test = test_builder
+
+cwd = os.getcwd()
+os.chdir(str(Dir('.').srcdir))
+scripts = glob.glob('*/SConscript')
+os.chdir(cwd)
+
+for s in scripts:
+    SConscript(s, exports = 'env', duplicate = False)
+
+# Set up phony commands for various test categories
+allTests = []
+for (key, val) in env.Tests.iteritems():
+    env.Command(key, val, env.NoAction)
+    allTests += val
+
+# The 'all' target is redundant since just specifying the test
+# directory name (e.g., ALPHA_SE/test/opt) has the same effect.
+env.Command('all', allTests, env.NoAction)
diff --git a/tests/diff-out b/tests/diff-out
new file mode 100755
index 000000000..5ebe97dd7
--- /dev/null
+++ b/tests/diff-out
@@ -0,0 +1,409 @@
+#!/usr/bin/perl
+# Copyright (c) 2001-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+#
+# This script diffs two SimpleScalar statistics output files.
+#
+
+use Getopt::Std;
+
+#
+# -t thresh sets threshold for ignoring differences (in %)
+# -p sorts differences by % chg (default is alphabetic)
+# -f ignores fetch-loss statistics
+# -d ignores all distributions
+#
+
+getopts('dfn:pt:h');
+
+if ($#ARGV < 1)
+{
+    print "\nError: need two file arguments (<reference> <new>).\n";
+    print "   Options: -d  =  Ignore distributions\n";
+    print "            -f  =  Ignore fetch-loss stats\n";
+    print "            -p  =  Sort errors by percentage\n";
+    print "            -h  =  Diff header info separately from stats\n";
+    print "            -n <num>  =  Print top <num> errors (default 20)\n";
+    print "            -t <num>  =  Error threshold in percent (default 1)\n\n";
+    die -1;
+}
+
+open(REF, "<$ARGV[0]") or die "Error: can't open $ARGV[0].\n";
+open(NEW, "<$ARGV[1]") or die "Error: can't open $ARGV[1].\n";
+
+
+#
+# Things that really should be adjustable via the command line
+#
+
+# Ignorable error (in percent)
+$err_thresh = ($opt_t) ? $opt_t : 0;
+
+# Number of stats to print before omitting
+$omit_count = ($opt_n) ? $opt_n : 20;
+
+
+#
+# First copy everything up to the simulation statistics to a pair of
+# temporary files, stripping out date-related items, and do a plain
+# diff.  Any differences in the arguments are not necessarily an issue;
+# any differences in the program output should be caught by the EIO
+# mechanism if an EIO file is used.
+# 
+
+# copy_header takes input filehandle and output filename
+
+sub copy_header
+{
+    my ($inhandle, $outname) = @_;
+
+    open(OUTPUT, ">$outname") or die "Error: can't open $outname.\n";
+
+    while (<$inhandle>)
+    {
+	# strip out lines that can vary
+	next if /^(command line:|M5 compiled on |M5 simulation started |M5 executing on )/;
+	last if /Begin Simulation Statistics/;
+	print OUTPUT;
+    }
+    close OUTPUT;
+}
+
+if ($opt_h) {
+
+    # Diff header separately from stats
+
+    $refheader = "/tmp/smt-test.refheader.$$";
+    $newheader = "/tmp/smt-test.newheader.$$";
+
+    copy_header(\*REF, $refheader);
+    copy_header(\*NEW, $newheader);
+
+    print "\n===== Header and program output differences =====\n\n";
+
+    print `diff $refheader $newheader`;
+
+    print "\n===== Statistics differences =====\n\n";
+}
+
+#
+# Now parse statistics
+#
+
+#
+# This function takes an open filehandle and returns a reference to
+# a hash containing all the statistics variables and their values.
+#
+sub parse_file
+{
+    $stathandle = shift;
+
+    $in_dist = undef;
+    $hashref = { };	# initialize hash for values
+
+    while (<$stathandle>)
+    {
+	next if /^\s*$/;	# skip blank lines
+                next if /^\*\*Ignore/;   # temporary, to make totaling scripts easy for ISCA 03
+	last if /End Simulation Statistics/;
+
+	s/ *#.*//;		# strip comments
+
+	if (/^Memory usage: (\d+) KBytes/) {
+	    $stat = 'memory usage';
+	    $value = $1;
+	}
+	elsif ($in_dist) {
+	    if ($in_dist =~ /^fetch_loss_counters/) {
+		if (/^fetch_loss_counters_\d+\.end/) {
+		    # end line of distribution: clear $in_dist flag
+		    $in_dist = undef;
+		    next;
+		}
+		else {
+		    next if $opt_f;
+
+		    ($stat, $value) = /^(\S+)\s+(.*)/;
+		}
+	    }
+	    else {
+		if (/(.*)\.end_dist/) {
+		    # end line of distribution: clear $in_dist flag
+		    $in_dist = undef;
+		    next;
+		}
+		if ($opt_d) {
+		    next;  #  bail out if we are ignoring dists...
+		}
+		elsif (/(.*)\.(min|max)_value/) {
+		    # treat these like normal stats
+		    ($stat, $value) = /^(\S+)\s+(.*)/;
+		}
+		else {
+		    # this is ugly because labels in the distribution
+		    # buckets don't start in column 0 and may include
+		    # embedded spaces
+		    ($stat, $value) =
+		      /^\s*(\S+(?:.*\S)?)\s+(\d+)\s+\d+\.\d+%/;
+		    $stat = $in_dist . '::' . $stat;
+		}
+	    }
+	}
+	else {
+	    if (/(.*)\.start_dist/) {
+		# start line of distribution: set $in_dist flag
+		# and save distribution name for future reference
+		$in_dist = $1;
+		$stat = $1;
+		$value = 0;
+	    }
+	    elsif (/^(fetch_loss_counters_\d+)\.start/) {
+		# treat fetch loss counters like distribution, sort of
+		$in_dist = $1;
+		$stat = $1;
+		$value = 0;
+	    }
+	    else {
+		($stat, $value) = /^(\S+)\s+(.*)/;
+	    }
+	}
+
+	$$hashref{$stat} = $value;
+    }
+
+    close($stathandle);
+    return $hashref;
+}
+
+
+#
+# pct_diff($old, $new) returns percent difference from $old to $new.
+#
+sub pct_diff
+{
+    my ($old, $new) = @_;
+    return ($old == 0) ? (($new == 0) ? 0 : 9999) : 100 * ($new - $old) / $old;
+}
+
+
+#
+# Statistics to ignore: these relate to simulator performance, not
+# correctness, so don't fail on changes here.
+#
+%ignore = (
+  'host_seconds' => 1,
+  'host_tick_rate' => 1,
+  'host_inst_rate' => 1,
+  'host_mem_usage' => 1
+);
+
+#
+# List of key statistics (always displayed)
+#  ==> list stats here WITHOUT trailing thread ID
+#
+@key_stat_list = (
+  'COM:IPC',
+  'ISSUE:MSIPC',
+  'COM:count',
+  'host_inst_rate',
+  'sim_insts',
+  'sim_ticks',
+  'host_mem_usage'
+);
+
+$key_stat_pattern = join('|', @key_stat_list);
+
+# initialize first statistics from each file
+
+$max_err_mag = 0;
+
+$refhash = parse_file(\*REF);
+$newhash = parse_file(\*NEW);
+
+# The string sim-smt prints on a divide by zero
+$divbyzero = '<err: divide by zero>';
+
+foreach $stat (sort keys %$refhash)
+{
+    $refvalue = $$refhash{$stat};
+    $newvalue = $$newhash{$stat};
+
+    if (!defined($newvalue)) {
+	# stat missing from new file
+	push @missing_stats, $stat;
+	next;
+    }
+
+    if ($stat =~ /($key_stat_pattern)/o) {
+	# key statistics: always record & display changes in these
+	push @key_stats, [$stat, $refvalue, $newvalue];
+    }
+
+    if ($ignore{$stat} or $refvalue eq $newvalue) {
+	# stat is in "ignore" list, or hasn't changed
+    }
+    else {
+	if ($refvalue eq $divbyzero || $newvalue eq $divbyzero) {
+	    # one or the other was a divide by zero:
+	    # no point in trying to quantify error
+	    print "$stat: $refvalue --> $newvalue\n";
+	}
+	else {
+	    $reldiff = pct_diff($refvalue, $newvalue);
+	    $diffmag = abs($reldiff);
+
+	    if ($diffmag > $err_thresh) {
+		push @errs,
+		[$stat, $refvalue, $newvalue, $reldiff];
+	    }
+
+	    if ($diffmag > $max_err_mag) {
+		$max_err_mag = $diffmag;
+	    }
+	}
+    }
+
+    # remove from new hash so we can detect added stats
+    delete $$newhash{$stat};
+}
+
+
+#
+# All done.  Print comparison summary.
+#
+
+printf("Maximum error magnitude: %+f%%\n\n", $max_err_mag);
+
+printf("  %-30s %10s %10s %10s   %7s\n", ' ', 'Reference', 'New Value', 'Abs Diff', 'Pct Chg');
+
+printf("Key statistics:\n\n");
+
+foreach $key_stat (@key_stats)
+{
+    ($statname, $refvalue, $newvalue, $reldiff) = @$key_stat;
+
+    # deduce format from reference value
+    $pointpos = rindex($refvalue, '.');
+    $digits = ($pointpos < 0) ? 0 :(length($refvalue) - $pointpos - 1);
+    $fmt = "%10.${digits}f";
+
+    # print differing values with absolute and relative error
+    printf("  %-30s $fmt $fmt $fmt  %+7.2f%%\n",
+	   $statname, $refvalue, $newvalue,
+	   $newvalue - $refvalue, pct_diff($refvalue, $newvalue));
+}
+
+printf("\nLargest $omit_count relative errors (> %d%%):\n\n", $err_thresh);
+
+$num_errs = 0;
+
+if ($opt_p)
+{
+    # sort differences by percent change
+    @errs = sort { abs($$b[3]) <=> abs($$a[3]) } @errs;
+}
+
+foreach $err (@errs)
+{
+    ($statname, $refvalue, $newvalue, $reldiff) = @$err;
+
+    # deduce format from reference value
+    $pointpos1 = rindex($refvalue, '.');
+    $digits1 = ($pointpos1 < 0) ? 0 :(length($refvalue) - $pointpos1 - 1);
+    $pointpos2 = rindex($newvalue, '.');
+    $digits2 = ($pointpos2 < 0) ? 0 :(length($newvalue) - $pointpos2 - 1);
+    $digits = ($digits1 > $digits2) ? $digits1 : $digits2;
+    $fmt = "%10.${digits}f";
+
+    # print differing values with absolute and relative error
+    printf("  %-30s $fmt $fmt $fmt  %+7.2f%%\n",
+	   $statname, $refvalue, $newvalue, $newvalue - $refvalue, $reldiff);
+
+    # only print top N errors
+    if (++$num_errs >= $omit_count)
+    {
+	print "[... additional errors omitted ...]\n";
+	last;
+    }
+}
+
+#
+# Report missing stats, but first filter out distribution buckets:
+# these are mostly noise
+
+@missing_stats = grep { !/::(\d+|overflows)?$/ } @missing_stats;
+
+# get count
+$missing_stats = scalar(@missing_stats);
+
+if ($missing_stats)
+{
+    print "\nMissing $missing_stats reference statistics:\n\n";
+    foreach $stat (@missing_stats)
+    {
+#	print "\t$stat\n";
+	printf "  %-50s    ", $stat;
+	print  "$$refhash{$stat}\n";
+    }
+}
+
+#
+# Any stats left in newhash are added since the reference file
+#
+
+@added_stats = keys %$newhash;
+
+# first filter out distribution buckets: mostly noise
+
+@added_stats = grep { !/::(\d+|overflows)?$/ } @added_stats;
+
+# get count
+$added_stats = scalar(@added_stats);
+
+if ($added_stats)
+{
+    print "\nFound $added_stats new statistics:\n\n";
+    foreach $stat (sort @added_stats)
+    {
+#	print "\t$stat\n";
+	printf "  %-50s    ", $stat;
+	print  "$$newhash{$stat}\n";
+    }
+}
+
+cleanup();
+# Exit code is 0 if no stats error, 1 otherwise
+$status = ($max_err_mag == 0.0) ? 0 : 1;
+exit $status;
+
+sub cleanup
+{
+    unlink($refheader) if ($refheader);
+    unlink($newheader) if ($newheader);
+}
diff --git a/tests/test1/ref/alpha/atomic/config.ini b/tests/test1/ref/alpha/atomic/config.ini
new file mode 100644
index 000000000..9961fe389
--- /dev/null
+++ b/tests/test1/ref/alpha/atomic/config.ini
@@ -0,0 +1,95 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu0 physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=mem
+clock=1
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu0.mem
+simulate_stalls=false
+system=system
+width=1
+workload=system.workload
+
+[system.cpu0.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/test1/ref/alpha/atomic/config.out b/tests/test1/ref/alpha/atomic/config.out
new file mode 100644
index 000000000..a9c04ceff
--- /dev/null
+++ b/tests/test1/ref/alpha/atomic/config.out
@@ -0,0 +1,90 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu0.mem]
+type=Bus
+bus_id=0
+
+[system.cpu0]
+type=AtomicSimpleCPU
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.cpu0.mem
+system=system
+workload=system.workload
+clock=1
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
diff --git a/tests/test1/ref/alpha/atomic/m5stats.txt b/tests/test1/ref/alpha/atomic/m5stats.txt
new file mode 100644
index 000000000..09e94d639
--- /dev/null
+++ b/tests/test1/ref/alpha/atomic/m5stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                1301768                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147756                       # Number of bytes of host memory used
+host_seconds                                     0.38                       # Real time elapsed on the host
+host_tick_rate                                1300060                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                      500000                       # Number of instructions simulated
+sim_seconds                                  0.000000                       # Number of seconds simulated
+sim_ticks                                      499999                       # Number of ticks simulated
+system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu0.numCycles                          500000                       # number of cpu cycles simulated
+system.cpu0.num_insts                          500000                       # Number of instructions executed
+system.cpu0.num_refs                           182204                       # Number of memory references
+system.workload.PROG:num_syscalls                  18                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/test1/ref/alpha/atomic/stderr b/tests/test1/ref/alpha/atomic/stderr
new file mode 100644
index 000000000..4e444fa6b
--- /dev/null
+++ b/tests/test1/ref/alpha/atomic/stderr
@@ -0,0 +1,3 @@
+warn: Entering event queue @ 0.  Starting simulation...
+
+gzip: stdout: Broken pipe
diff --git a/tests/test1/ref/alpha/atomic/stdout b/tests/test1/ref/alpha/atomic/stdout
new file mode 100644
index 000000000..78ab05bdd
--- /dev/null
+++ b/tests/test1/ref/alpha/atomic/stdout
@@ -0,0 +1,14 @@
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 19 2006 15:49:01
+M5 started Wed Jul 19 15:49:10 2006
+M5 executing on zamp.eecs.umich.edu
+Creating SE system
+Exiting @ tick 499999 because a thread reached the max instruction count
diff --git a/tests/test1/ref/alpha/detailed/config.ini b/tests/test1/ref/alpha/detailed/config.ini
new file mode 100644
index 000000000..192833c8b
--- /dev/null
+++ b/tests/test1/ref/alpha/detailed/config.ini
@@ -0,0 +1,298 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu0 physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu0]
+type=DerivO3CPU
+children=checker fuPool mem
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+checker=system.cpu0.checker
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu0.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu0.mem
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numThreads=1
+predType=tournament
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+wbDepth=1
+wbWidth=8
+workload=system.workload
+
+[system.cpu0.checker]
+type=O3Checker
+clock=1
+defer_registration=false
+exitOnError=true
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+system=system
+warnOnlyOnLoadError=false
+workload=system.workload
+
+[system.cpu0.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
+
+[system.cpu0.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu0.fuPool.FUList0.opList0
+
+[system.cpu0.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu0.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
+
+[system.cpu0.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu0.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu0.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
+
+[system.cpu0.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu0.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu0.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu0.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
+
+[system.cpu0.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu0.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu0.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu0.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu0.fuPool.FUList4.opList0
+
+[system.cpu0.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu0.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu0.fuPool.FUList5.opList0
+
+[system.cpu0.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu0.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
+
+[system.cpu0.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu0.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu0.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu0.fuPool.FUList7.opList0
+
+[system.cpu0.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu0.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/test1/ref/alpha/detailed/config.out b/tests/test1/ref/alpha/detailed/config.out
new file mode 100644
index 000000000..07c092a2b
--- /dev/null
+++ b/tests/test1/ref/alpha/detailed/config.out
@@ -0,0 +1,293 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu0.mem]
+type=Bus
+bus_id=0
+
+[system.cpu0.checker]
+type=O3Checker
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+workload=system.workload
+clock=1
+defer_registration=false
+exitOnError=true
+warnOnlyOnLoadError=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu0.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu0.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu0.fuPool.FUList0.opList0
+count=6
+
+[system.cpu0.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu0.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu0.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
+count=2
+
+[system.cpu0.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu0.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu0.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu0.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
+count=4
+
+[system.cpu0.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu0.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu0.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu0.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
+count=2
+
+[system.cpu0.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu0.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu0.fuPool.FUList4.opList0
+count=0
+
+[system.cpu0.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu0.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu0.fuPool.FUList5.opList0
+count=0
+
+[system.cpu0.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu0.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu0.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
+count=4
+
+[system.cpu0.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu0.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu0.fuPool.FUList7.opList0
+count=1
+
+[system.cpu0.fuPool]
+type=FUPool
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
+
+[system.cpu0]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.workload
+mem=system.cpu0.mem
+checker=system.cpu0.checker
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu0.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=6
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
diff --git a/tests/test1/ref/alpha/detailed/m5stats.txt b/tests/test1/ref/alpha/detailed/m5stats.txt
new file mode 100644
index 000000000..8ff727085
--- /dev/null
+++ b/tests/test1/ref/alpha/detailed/m5stats.txt
@@ -0,0 +1,1775 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits                        45390                       # Number of BTB hits
+global.BPredUnit.BTBLookups                     59902                       # Number of BTB lookups
+global.BPredUnit.RASInCorrect                      85                       # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect                   3098                       # Number of conditional branches incorrect
+global.BPredUnit.condPredicted                  46029                       # Number of conditional branches predicted
+global.BPredUnit.lookups                        70231                       # Number of BP lookups
+global.BPredUnit.usedRAS                         7755                       # Number of times the RAS was used to get a target.
+host_inst_rate                                  69741                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 148316                       # Number of bytes of host memory used
+host_seconds                                     7.17                       # Real time elapsed on the host
+host_tick_rate                                  36160                       # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads              15235                       # Number of conflicting loads.
+memdepunit.memDep.conflictingStores              2693                       # Number of conflicting stores.
+memdepunit.memDep.insertedLoads                145639                       # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores                60928                       # Number of stores inserted to the mem dependence unit.
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                      500002                       # Number of instructions simulated
+sim_seconds                                  0.000000                       # Number of seconds simulated
+sim_ticks                                      259259                       # Number of ticks simulated
+system.cpu0.checker.numCycles                  518940                       # number of cpu cycles simulated
+system.cpu0.commit.COM:branches                 61160                       # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events            17172                       # number cycles where commit BW limit reached
+system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
+system.cpu0.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle.samples       251997                      
+system.cpu0.commit.COM:committed_per_cycle.min_value            0                      
+                               0        70509   2798.01%           
+                               1        75489   2995.63%           
+                               2        28876   1145.89%           
+                               3        23224    921.60%           
+                               4        21222    842.15%           
+                               5         3198    126.91%           
+                               6         8368    332.07%           
+                               7         3939    156.31%           
+                               8        17172    681.44%           
+system.cpu0.commit.COM:committed_per_cycle.max_value            8                      
+system.cpu0.commit.COM:committed_per_cycle.end_dist
+
+system.cpu0.commit.COM:count                   518948                       # Number of instructions committed
+system.cpu0.commit.COM:loads                   131376                       # Number of loads committed
+system.cpu0.commit.COM:membars                      0                       # Number of memory barriers committed
+system.cpu0.commit.COM:refs                    189772                       # Number of memory references committed
+system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
+system.cpu0.commit.branchMispredicts             2836                       # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts        518948                       # The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls             18                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts          44297                       # The number of squashed insts skipped by commit
+system.cpu0.committedInsts                     500002                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total               500002                       # Number of Instructions Simulated
+system.cpu0.cpi                              0.518516                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.518516                       # CPI: Total CPI of All Threads
+system.cpu0.decode.DECODE:BlockedCycles           743                       # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:BranchMispred           281                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DECODE:BranchResolved        16033                       # Number of times decode resolved a branch
+system.cpu0.decode.DECODE:DecodedInsts         586219                       # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles           143055                       # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles            108199                       # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles           7263                       # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:SquashedInsts           989                       # Number of squashed instructions handled by decode
+system.cpu0.fetch.Branches                      70231                       # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines                    71036                       # Number of cache lines fetched
+system.cpu0.fetch.Cycles                       180480                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes                  962                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts                        594968                       # Number of instructions fetch has processed
+system.cpu0.fetch.SquashCycles                   3140                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate                 0.270890                       # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles             71036                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches             53145                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate                       2.294870                       # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist.start_dist                          # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist.samples             259260                      
+system.cpu0.fetch.rateDist.min_value                0                      
+                               0       149817   5778.64%           
+                               1         3603    138.97%           
+                               2         9058    349.38%           
+                               3        10685    412.13%           
+                               4         8455    326.12%           
+                               5        18775    724.18%           
+                               6        25664    989.89%           
+                               7         6109    235.63%           
+                               8        27094   1045.05%           
+system.cpu0.fetch.rateDist.max_value                8                      
+system.cpu0.fetch.rateDist.end_dist
+
+system.cpu0.iew.EXEC:branches                   64672                       # Number of branches executed
+system.cpu0.iew.EXEC:insts                     526242                       # Number of executed instructions
+system.cpu0.iew.EXEC:loads                     140576                       # Number of load instructions executed
+system.cpu0.iew.EXEC:nop                        19405                       # number of nop insts executed
+system.cpu0.iew.EXEC:rate                    2.029785                       # Inst execution rate
+system.cpu0.iew.EXEC:refs                      200121                       # number of memory reference insts executed
+system.cpu0.iew.EXEC:squashedInsts               5760                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.EXEC:stores                     59545                       # Number of stores executed
+system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
+system.cpu0.iew.WB:consumers                   394903                       # num instructions consuming a value
+system.cpu0.iew.WB:count                       523588                       # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout                    0.746115                       # average fanout of values written-back
+system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.iew.WB:producers                   294643                       # num instructions producing a value
+system.cpu0.iew.WB:rate                      2.019548                       # insts written-back per cycle
+system.cpu0.iew.WB:sent                        524223                       # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts                2948                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles                      0                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts               145639                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispNonSpecInsts                27                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispSquashedInsts             1523                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts               60928                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts             563297                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewIQFullEvents                     0                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles                  7263                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles                    0                       # Number of cycles IEW is unblocking
+system.cpu0.iew.lsq.thread.0.blockedLoads            1                       # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads          18223                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses            9                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread.0.rescheduledLoads            1                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread.0.squashedLoads        14246                       # Number of loads squashed
+system.cpu0.iew.lsq.thread.0.squashedStores         2528                       # Number of stores squashed
+system.cpu0.iew.memOrderViolationEvents            44                       # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect         1750                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect          1198                       # Number of branches that were predicted taken incorrectly
+system.cpu0.ipc                              1.928581                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.928581                       # IPC: Total IPC of All Threads
+system.cpu0.iq.IQ:residence:(null).start_dist                     # cycles from dispatch to issue
+system.cpu0.iq.IQ:residence:(null).samples            0                      
+system.cpu0.iq.IQ:residence:(null).min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.IQ:residence:(null).max_value            0                      
+system.cpu0.iq.IQ:residence:(null).end_dist
+
+system.cpu0.iq.IQ:residence:IntAlu.start_dist                     # cycles from dispatch to issue
+system.cpu0.iq.IQ:residence:IntAlu.samples            0                      
+system.cpu0.iq.IQ:residence:IntAlu.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.IQ:residence:IntAlu.max_value            0                      
+system.cpu0.iq.IQ:residence:IntAlu.end_dist
+
+system.cpu0.iq.IQ:residence:IntMult.start_dist                     # cycles from dispatch to issue
+system.cpu0.iq.IQ:residence:IntMult.samples            0                      
+system.cpu0.iq.IQ:residence:IntMult.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.IQ:residence:IntMult.max_value            0                      
+system.cpu0.iq.IQ:residence:IntMult.end_dist
+
+system.cpu0.iq.IQ:residence:IntDiv.start_dist                     # cycles from dispatch to issue
+system.cpu0.iq.IQ:residence:IntDiv.samples            0                      
+system.cpu0.iq.IQ:residence:IntDiv.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.IQ:residence:IntDiv.max_value            0                      
+system.cpu0.iq.IQ:residence:IntDiv.end_dist
+
+system.cpu0.iq.IQ:residence:FloatAdd.start_dist                     # cycles from dispatch to issue
+system.cpu0.iq.IQ:residence:FloatAdd.samples            0                      
+system.cpu0.iq.IQ:residence:FloatAdd.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.IQ:residence:FloatAdd.max_value            0                      
+system.cpu0.iq.IQ:residence:FloatAdd.end_dist
+
+system.cpu0.iq.IQ:residence:FloatCmp.start_dist                     # cycles from dispatch to issue
+system.cpu0.iq.IQ:residence:FloatCmp.samples            0                      
+system.cpu0.iq.IQ:residence:FloatCmp.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.IQ:residence:FloatCmp.max_value            0                      
+system.cpu0.iq.IQ:residence:FloatCmp.end_dist
+
+system.cpu0.iq.IQ:residence:FloatCvt.start_dist                     # cycles from dispatch to issue
+system.cpu0.iq.IQ:residence:FloatCvt.samples            0                      
+system.cpu0.iq.IQ:residence:FloatCvt.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.IQ:residence:FloatCvt.max_value            0                      
+system.cpu0.iq.IQ:residence:FloatCvt.end_dist
+
+system.cpu0.iq.IQ:residence:FloatMult.start_dist                     # cycles from dispatch to issue
+system.cpu0.iq.IQ:residence:FloatMult.samples            0                      
+system.cpu0.iq.IQ:residence:FloatMult.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
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+                              98            0                      
+system.cpu0.iq.ISSUE:FloatMult_delay.max_value            0                      
+system.cpu0.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu0.iq.ISSUE:FloatDiv_delay.start_dist                     # cycles from operands ready to issue
+system.cpu0.iq.ISSUE:FloatDiv_delay.samples            0                      
+system.cpu0.iq.ISSUE:FloatDiv_delay.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.ISSUE:FloatDiv_delay.max_value            0                      
+system.cpu0.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu0.iq.ISSUE:FloatSqrt_delay.start_dist                     # cycles from operands ready to issue
+system.cpu0.iq.ISSUE:FloatSqrt_delay.samples            0                      
+system.cpu0.iq.ISSUE:FloatSqrt_delay.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.ISSUE:FloatSqrt_delay.max_value            0                      
+system.cpu0.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu0.iq.ISSUE:MemRead_delay.start_dist                     # cycles from operands ready to issue
+system.cpu0.iq.ISSUE:MemRead_delay.samples            0                      
+system.cpu0.iq.ISSUE:MemRead_delay.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.ISSUE:MemRead_delay.max_value            0                      
+system.cpu0.iq.ISSUE:MemRead_delay.end_dist
+
+system.cpu0.iq.ISSUE:MemWrite_delay.start_dist                     # cycles from operands ready to issue
+system.cpu0.iq.ISSUE:MemWrite_delay.samples            0                      
+system.cpu0.iq.ISSUE:MemWrite_delay.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.ISSUE:MemWrite_delay.max_value            0                      
+system.cpu0.iq.ISSUE:MemWrite_delay.end_dist
+
+system.cpu0.iq.ISSUE:IprAccess_delay.start_dist                     # cycles from operands ready to issue
+system.cpu0.iq.ISSUE:IprAccess_delay.samples            0                      
+system.cpu0.iq.ISSUE:IprAccess_delay.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.ISSUE:IprAccess_delay.max_value            0                      
+system.cpu0.iq.ISSUE:IprAccess_delay.end_dist
+
+system.cpu0.iq.ISSUE:InstPrefetch_delay.start_dist                     # cycles from operands ready to issue
+system.cpu0.iq.ISSUE:InstPrefetch_delay.samples            0                      
+system.cpu0.iq.ISSUE:InstPrefetch_delay.min_value            0                      
+                               0            0                      
+                               2            0                      
+                               4            0                      
+                               6            0                      
+                               8            0                      
+                              10            0                      
+                              12            0                      
+                              14            0                      
+                              16            0                      
+                              18            0                      
+                              20            0                      
+                              22            0                      
+                              24            0                      
+                              26            0                      
+                              28            0                      
+                              30            0                      
+                              32            0                      
+                              34            0                      
+                              36            0                      
+                              38            0                      
+                              40            0                      
+                              42            0                      
+                              44            0                      
+                              46            0                      
+                              48            0                      
+                              50            0                      
+                              52            0                      
+                              54            0                      
+                              56            0                      
+                              58            0                      
+                              60            0                      
+                              62            0                      
+                              64            0                      
+                              66            0                      
+                              68            0                      
+                              70            0                      
+                              72            0                      
+                              74            0                      
+                              76            0                      
+                              78            0                      
+                              80            0                      
+                              82            0                      
+                              84            0                      
+                              86            0                      
+                              88            0                      
+                              90            0                      
+                              92            0                      
+                              94            0                      
+                              96            0                      
+                              98            0                      
+system.cpu0.iq.ISSUE:InstPrefetch_delay.max_value            0                      
+system.cpu0.iq.ISSUE:InstPrefetch_delay.end_dist
+
+system.cpu0.iq.ISSUE:FU_type_0                 532005                       # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0.start_dist
+                          (null)            0      0.00%            # Type of FU issued
+                          IntAlu       329259     61.89%            # Type of FU issued
+                         IntMult           10      0.00%            # Type of FU issued
+                          IntDiv            0      0.00%            # Type of FU issued
+                        FloatAdd           13      0.00%            # Type of FU issued
+                        FloatCmp            3      0.00%            # Type of FU issued
+                        FloatCvt            0      0.00%            # Type of FU issued
+                       FloatMult            2      0.00%            # Type of FU issued
+                        FloatDiv            0      0.00%            # Type of FU issued
+                       FloatSqrt            0      0.00%            # Type of FU issued
+                         MemRead       142868     26.85%            # Type of FU issued
+                        MemWrite        59850     11.25%            # Type of FU issued
+                       IprAccess            0      0.00%            # Type of FU issued
+                    InstPrefetch            0      0.00%            # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0.end_dist
+system.cpu0.iq.ISSUE:fu_busy_cnt                 5510                       # FU busy when requested
+system.cpu0.iq.ISSUE:fu_busy_rate            0.010357                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.ISSUE:fu_full.start_dist
+                          (null)            0      0.00%            # attempts to use FU when none available
+                          IntAlu         1663     30.18%            # attempts to use FU when none available
+                         IntMult            0      0.00%            # attempts to use FU when none available
+                          IntDiv            0      0.00%            # attempts to use FU when none available
+                        FloatAdd            0      0.00%            # attempts to use FU when none available
+                        FloatCmp            0      0.00%            # attempts to use FU when none available
+                        FloatCvt            0      0.00%            # attempts to use FU when none available
+                       FloatMult            0      0.00%            # attempts to use FU when none available
+                        FloatDiv            0      0.00%            # attempts to use FU when none available
+                       FloatSqrt            0      0.00%            # attempts to use FU when none available
+                         MemRead         2693     48.87%            # attempts to use FU when none available
+                        MemWrite         1154     20.94%            # attempts to use FU when none available
+                       IprAccess            0      0.00%            # attempts to use FU when none available
+                    InstPrefetch            0      0.00%            # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full.end_dist
+system.cpu0.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle.samples       259260                      
+system.cpu0.iq.ISSUE:issued_per_cycle.min_value            0                      
+                               0        59185   2282.84%           
+                               1        72964   2814.32%           
+                               2        38364   1479.75%           
+                               3        33144   1278.41%           
+                               4        19818    764.41%           
+                               5        14624    564.07%           
+                               6        18233    703.27%           
+                               7         2333     89.99%           
+                               8          595     22.95%           
+system.cpu0.iq.ISSUE:issued_per_cycle.max_value            8                      
+system.cpu0.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu0.iq.ISSUE:rate                    2.052013                       # Inst issue rate
+system.cpu0.iq.iqInstsAdded                    543865                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued                   532005                       # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded                 27                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined          42716                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued              611                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved             9                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined        21818                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.numCycles                          259260                       # number of cpu cycles simulated
+system.cpu0.rename.RENAME:BlockCycles             191                       # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps        386063                       # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IdleCycles           144885                       # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents           336                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:RenameLookups        753146                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts         577319                       # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands       432146                       # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles            106374                       # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles           7263                       # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles           302                       # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps            46034                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:serializeStallCycles          245                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts           34                       # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts               421                       # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts           32                       # count of temporary serializing insts renamed
+system.workload.PROG:num_syscalls                  18                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/test1/ref/alpha/detailed/stderr b/tests/test1/ref/alpha/detailed/stderr
new file mode 100644
index 000000000..2b973e482
--- /dev/null
+++ b/tests/test1/ref/alpha/detailed/stderr
@@ -0,0 +1,4 @@
+warn: Entering event queue @ 0.  Starting simulation...
+warn: cycle 0: fault (1) detected @ PC 0x000000
+
+gzip: stdout: Broken pipe
diff --git a/tests/test1/ref/alpha/detailed/stdout b/tests/test1/ref/alpha/detailed/stdout
new file mode 100644
index 000000000..2c46aa4f2
--- /dev/null
+++ b/tests/test1/ref/alpha/detailed/stdout
@@ -0,0 +1,14 @@
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 19 2006 15:49:01
+M5 started Wed Jul 19 15:49:12 2006
+M5 executing on zamp.eecs.umich.edu
+Creating SE system
+Exiting @ tick 259259 because a thread reached the max instruction count
diff --git a/tests/test1/ref/alpha/timing/config.ini b/tests/test1/ref/alpha/timing/config.ini
new file mode 100644
index 000000000..58dc6741b
--- /dev/null
+++ b/tests/test1/ref/alpha/timing/config.ini
@@ -0,0 +1,93 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu0 physmem workload
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=mem
+clock=1
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu0.mem
+system=system
+workload=system.workload
+
+[system.cpu0.mem]
+type=Bus
+bus_id=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+
+[system.workload]
+type=EioProcess
+chkpt=
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+output=cout
+system=system
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/test1/ref/alpha/timing/config.out b/tests/test1/ref/alpha/timing/config.out
new file mode 100644
index 000000000..b28de6f74
--- /dev/null
+++ b/tests/test1/ref/alpha/timing/config.out
@@ -0,0 +1,90 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+// range not specified
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.workload]
+type=EioProcess
+file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu0.mem]
+type=Bus
+bus_id=0
+
+[system.cpu0]
+type=TimingSimpleCPU
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+mem=system.cpu0.mem
+system=system
+workload=system.workload
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
diff --git a/tests/test1/ref/alpha/timing/m5stats.txt b/tests/test1/ref/alpha/timing/m5stats.txt
new file mode 100644
index 000000000..64d05099f
--- /dev/null
+++ b/tests/test1/ref/alpha/timing/m5stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                 739858                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147760                       # Number of bytes of host memory used
+host_seconds                                     0.68                       # Real time elapsed on the host
+host_tick_rate                                1006609                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                      500000                       # Number of instructions simulated
+sim_seconds                                  0.000001                       # Number of seconds simulated
+sim_ticks                                      680774                       # Number of ticks simulated
+system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
+system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
+system.cpu0.numCycles                               0                       # number of cpu cycles simulated
+system.cpu0.num_insts                          500000                       # Number of instructions executed
+system.cpu0.num_refs                           182203                       # Number of memory references
+system.workload.PROG:num_syscalls                  18                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/test1/ref/alpha/timing/stderr b/tests/test1/ref/alpha/timing/stderr
new file mode 100644
index 000000000..4e444fa6b
--- /dev/null
+++ b/tests/test1/ref/alpha/timing/stderr
@@ -0,0 +1,3 @@
+warn: Entering event queue @ 0.  Starting simulation...
+
+gzip: stdout: Broken pipe
diff --git a/tests/test1/ref/alpha/timing/stdout b/tests/test1/ref/alpha/timing/stdout
new file mode 100644
index 000000000..980af1477
--- /dev/null
+++ b/tests/test1/ref/alpha/timing/stdout
@@ -0,0 +1,14 @@
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 19 2006 15:49:01
+M5 started Wed Jul 19 15:49:19 2006
+M5 executing on zamp.eecs.umich.edu
+Creating SE system
+Exiting @ tick 680774 because a thread reached the max instruction count