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authorRon Dreslinski <rdreslin@umich.edu>2007-03-12 13:15:32 -0500
committerRon Dreslinski <rdreslin@umich.edu>2007-03-12 13:15:32 -0500
commit6415c47a5b196beb16ee56c8cb772dd3fd53b687 (patch)
treec7a6619dee50bf7885b5b382eca34954698490b8
parent1aef5c06a3702d7722dcd38e342eae950839cecb (diff)
downloadgem5-6415c47a5b196beb16ee56c8cb772dd3fd53b687.tar.xz
Fix some of the memory leaks related to writebacks
src/cpu/memtest/memtest.cc: Add the [] to a delete to make it work correctly src/mem/cache/cache_impl.hh: Fix one of the memory leaks --HG-- extra : convert_revision : 64c7465c68a084efe38a62419205518b24d852a7
-rw-r--r--src/cpu/memtest/memtest.cc2
-rw-r--r--src/mem/cache/cache_impl.hh14
2 files changed, 11 insertions, 5 deletions
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 8b3e9a11e..607cf1066 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -369,7 +369,7 @@ MemTest::tick()
//This means we assume CPU does write forwarding to reads that alias something
//in the cpu store buffer.
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
- delete result;
+ delete [] result;
delete req;
return;
}
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 056f6033f..d8aab0e58 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -570,8 +570,10 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
}
}
while (!writebacks.empty()) {
- missQueue->doWriteback(writebacks.front());
+ PacketPtr wbPkt = writebacks.front();
+ missQueue->doWriteback(wbPkt);
writebacks.pop_front();
+ delete wbPkt;
}
DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(),
@@ -721,8 +723,10 @@ Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
blk = handleFill(blk, (MSHR*)pkt->senderState,
new_state, writebacks, pkt);
while (!writebacks.empty()) {
- missQueue->doWriteback(writebacks.front());
- writebacks.pop_front();
+ PacketPtr wbPkt = writebacks.front();
+ missQueue->doWriteback(wbPkt);
+ writebacks.pop_front();
+ delete wbPkt;
}
}
missQueue->handleResponse(pkt, curTick + hitLatency);
@@ -1040,8 +1044,10 @@ return 0;
// There was a cache hit.
// Handle writebacks if needed
while (!writebacks.empty()){
- memSidePort->sendAtomic(writebacks.front());
+ PacketPtr wbPkt = writebacks.front();
+ memSidePort->sendAtomic(wbPkt);
writebacks.pop_front();
+ delete wbPkt;
}
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;