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authorAndreas Hansson <andreas.hansson@arm.com>2014-11-14 03:53:48 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2014-11-14 03:53:48 -0500
commit9ffe0e7ba67ee194db885b96a7ed3630aed03584 (patch)
tree46deaf5903e5990f30f8c9c26b928f3b08ddb43e
parent4583a5114aa34efb3b83e9a2e40dd74f7c49facb (diff)
downloadgem5-9ffe0e7ba67ee194db885b96a7ed3630aed03584.tar.xz
mem: Clarify unit of DRAM controller buffer size
-rw-r--r--src/mem/DRAMCtrl.py5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index 642e9d525..74fb7c7be 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -71,7 +71,10 @@ class DRAMCtrl(AbstractMemory):
# bus in front of the controller for multiple ports
port = SlavePort("Slave port")
- # the basic configuration of the controller architecture
+ # the basic configuration of the controller architecture, note
+ # that each entry corresponds to a burst for the specific DRAM
+ # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
+ # the cacheline size or request/packet size
write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
read_buffer_size = Param.Unsigned(32, "Number of read queue entries")