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author | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-04 08:34:16 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-04 08:34:16 -0400 |
commit | a07340f6cd24817222c1b8905f8a33015322b6bd (patch) | |
tree | e6d319afc2a411f55a5bd62d965f9fc9cdb2d78e | |
parent | a72deba7080ba933778ae2cb09e504beaad2009b (diff) | |
parent | 4889d8f78826331d567327535fcd481fa2caf939 (diff) | |
download | gem5-a07340f6cd24817222c1b8905f8a33015322b6bd.tar.xz |
Merge zizzer:/z/m5/Bitkeeper/m5
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/prefetcher
--HG--
extra : convert_revision : b89d95b6b09a70dc060747f9703643af008c2ddd
-rw-r--r-- | python/m5/objects/BaseCache.mpy | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index 198665325..3727f2f01 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -1,5 +1,7 @@ from BaseMem import BaseMem +class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] + simobj BaseCache(BaseMem): type = 'BaseCache' adaptive_compression = Param.Bool(False, @@ -44,4 +46,11 @@ simobj BaseCache(BaseMem): "Number of entries in the harware prefetch queue") prefetch_past_page = Param.Bool(False, "Allow prefetches to cross virtual page boundaries") - + prefetch_serial_squash = Param.Bool(False, + "Squash prefetches with a later time on a subsequent miss") + prefetch_degree = Param.Int(1, + "Degree of the prefetch depth") + prefetch_latency = Param.Tick(10, + "Latency of the prefetcher") + prefetch_policy = Param.Prefetch('none', + "Type of prefetcher to use") |