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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-08-28 15:34:34 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-10 09:24:23 +0000 |
| commit | a3e0eb0b24c0c7145bbf8a247178323f58760ad5 (patch) | |
| tree | 0c7797255b881afcdb0520d7554e2ccbd726a1e9 | |
| parent | 6b5d56b162057f05f0e0b59a2d1af57b1da76276 (diff) | |
| download | gem5-a3e0eb0b24c0c7145bbf8a247178323f58760ad5.tar.xz | |
dev-arm: Create a getter for ArmInterruptPin ID number
A pin owner might want to know which is the irq number
associated with the pin.
Change-Id: I095393d4d25efe13eb2a75a0b0b055d386c2c126
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12298
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/dev/arm/base_gic.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh index 73d73e471..c5dfa3e82 100644 --- a/src/dev/arm/base_gic.hh +++ b/src/dev/arm/base_gic.hh @@ -128,6 +128,9 @@ class ArmInterruptPin : public SimObject */ void setThreadContext(ThreadContext *tc); + /** Get interrupt number */ + uint32_t num() const { return intNum; } + /** Signal an interrupt */ virtual void raise() = 0; /** Clear a signalled interrupt */ |