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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:13 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:13 -0500 |
| commit | aec73ba6af62c8da66fb40e015671541708c1723 (patch) | |
| tree | 82f2c20a2ec4d48bd73f5445c0775e478f17c67a | |
| parent | 65a5177b53c53b287125cec3f207afeec648d488 (diff) | |
| download | gem5-aec73ba6af62c8da66fb40e015671541708c1723.tar.xz | |
ARM: Add a traceflag to print cpsr
| -rw-r--r-- | src/arch/arm/isa.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 8d547f9c6..ded463267 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -238,6 +238,8 @@ namespace ArmISA if (misc_reg == MISCREG_CPSR) { updateRegMap(val); CPSR cpsr = val; + DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", + cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); Addr npc = tc->readNextPC() & ~PcModeMask; if (cpsr.j) npc = npc | (ULL(1) << PcJBitShift); |