X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions.

--HG--
extra : convert_revision : 37c63b1133022fa3432888592f8c84785fb95091

3 files changed, 53 insertions, 30 deletions

diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index ac714b3ff..62b8c8d59 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -313,17 +313,18 @@
                 default: WarnUnimpl::call_far_Ap();
             }
             0x3: WarnUnimpl::fwait(); //aka wait
-            0x4: WarnUnimpl::pushf_Fv();
-            0x5: WarnUnimpl::popf_Fv();
-            //Both of these should be illegal only if CPUID.AHF64=0,
-            //according to sandpile.org
+            0x4: PUSHF();
+            0x5: POPF();
+            //The 64 bit versions of both of these should be illegal only
+            //if CPUID says it isn't supported. For now, we'll just assume
+            //that it's supported.
             0x6: decode MODE_SUBMODE {
-                0x0: UD2();
-                default: WarnUnimpl::sahf();
+                0x0: SAHF_64();
+                default: SAHF();
             }
             0x7: decode MODE_SUBMODE {
-                0x0: UD2();
-                default: WarnUnimpl::lahf();
+                0x0: LAHF_64();
+                default: LAHF();
             }
         }
         0x14: decode OPCODE_OP_BOTTOM3 {
diff --git a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
index c6f279a25..0915bf819 100644
--- a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
+++ b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
@@ -53,10 +53,28 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class LAHF(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SAHF(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop SAHF {
+    # This will fold to ah since this never executes in 64 bit mode.
+    ruflags rsp, dataSize=1
+};
+
+# This is allows the instruction to write to ah in 64 bit mode.
+def macroop SAHF_64 {
+    ruflags t1
+    slli t1, t1, 8
+    mov t1, t1, rax, dataSize=1
+    mov rax, rax, t1, dataSize=2
+};
+
+def macroop LAHF {
+    # This will fold to ah since this never executes in 64 bit mode.
+    wruflags rsp, t0, dataSize=1
+};
+
+# This is allows the instruction to read from ah in 64 bit mode.
+def macroop LAHF_64 {
+    srli t1, rax, 8, dataSize=2
+    wruflags t1, t0, dataSize=1
+};
+'''
diff --git a/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py b/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
index dbb6c34c4..87e9ef03a 100644
--- a/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
+++ b/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
@@ -53,18 +53,22 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class POPF(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class POPFD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class POPFQ(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHF(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHFD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class pushfq(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop PUSHF {
+    .adjust_env oszIn64Override
+
+    # This should really read the whole flags register, not just user flags.
+    ruflags t1
+    st t1, ss, [1, t0, rsp], "-env.dataSize"
+    subi rsp, rsp, dsz
+};
+
+def macroop POPF {
+    .adjust_env oszIn64Override
+
+    ld t1, ss, [1, t0, rsp]
+    addi rsp, rsp, dsz
+    # This should really write the whole flags register, not just user flags.
+    wruflags t1, t0
+};
+'''