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| author | Nathan Binkert <binkertn@umich.edu> | 2007-06-09 22:43:08 -0700 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2007-06-09 22:43:08 -0700 |
| commit | e9936a6250756f6ca0434842846051cc44da7312 (patch) | |
| tree | 2298822b6488fd19fc676fc997a04ac62fdd06c8 | |
| parent | 1493ceda8fe242776423e30f83db0774f6558ad4 (diff) | |
| download | gem5-e9936a6250756f6ca0434842846051cc44da7312.tar.xz | |
More realistic parameters
--HG--
extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f
| -rw-r--r-- | configs/example/memtest.py | 3 | ||||
| -rw-r--r-- | src/mem/cache/BaseCache.py | 3 |
2 files changed, 3 insertions, 3 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index 9fd943aaa..c28ffab10 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -82,8 +82,7 @@ cpus = [ MemTest(atomic=not options.timing, max_loads=options.maxloads, # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), - physmem = PhysicalMemory(latency = "50ps"), - membus = Bus(clock="500MHz", width=16)) + physmem = PhysicalMemory(latency = "50ns"), membus = Bus(clock="500MHz", width=16)) # l2cache & bus if options.caches: diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 4b98f6b30..32f3f0174 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -27,6 +27,7 @@ # Authors: Nathan Binkert from m5.params import * +from m5.proxy import Self from MemObject import MemObject class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] @@ -77,7 +78,7 @@ class BaseCache(MemObject): "Squash prefetches with a later time on a subsequent miss") prefetch_degree = Param.Int(1, "Degree of the prefetch depth") - prefetch_latency = Param.Tick(10, + prefetch_latency = Param.Latency(10 * Self.latency, "Latency of the prefetcher") prefetch_policy = Param.Prefetch('none', "Type of prefetcher to use") |