diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-24 23:20:27 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-24 23:20:27 -0700 |
| commit | 02d80c96b79b8ae4b6f99e657579f36d28844795 (patch) | |
| tree | f16ce564fdcc1a1aa866598fd7399153469a9c00 | |
| parent | 91cb532f9f44874e768ba749df03ca1f4dc07bc9 (diff) | |
| download | gem5-02d80c96b79b8ae4b6f99e657579f36d28844795.tar.xz | |
Move some common full-system CPU initialization from the
SimpleCPU & FullCPU constructors to AlphaISA::initCPU().
cpu/simple_cpu/simple_cpu.cc:
Move some common full-system CPU initialization from the
SimpleCPU & FullCPU constructors to AlphaISA::initCPU().
Make 'fault' local to SimpleCPU::tick.
cpu/simple_cpu/simple_cpu.hh:
Make 'fault' local to SimpleCPU::tick (not an object member).
--HG--
extra : convert_revision : e878dedfff06aac0548aca8b14d66c18b8916895
| -rw-r--r-- | arch/alpha/ev5.cc | 6 | ||||
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 15 | ||||
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.hh | 3 |
3 files changed, 10 insertions, 14 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index cc33f6890..7330d7ce0 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -47,6 +47,11 @@ void AlphaISA::initCPU(RegFile *regs) { initIPRs(regs); + // CPU comes up with PAL regs enabled + swap_palshadow(regs, true); + + regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault]; + regs->npc = regs->pc + sizeof(MachInst); } void @@ -97,6 +102,7 @@ AlphaISA::initIPRs(RegFile *regs) bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); ipr[IPR_PAL_BASE] = PAL_BASE; + ipr[IPR_MCSR] = 0x6; } diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 891e6cdb3..d3d9bc2ca 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -126,19 +126,10 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process, #ifdef FULL_SYSTEM xc = new ExecContext(this, 0, system, itb, dtb, mem); + // initialize CPU, including PC TheISA::initCPU(&xc->regs); - - IntReg *ipr = xc->regs.ipr; - ipr[TheISA::IPR_MCSR] = 0x6; - - AlphaISA::swap_palshadow(&xc->regs, true); - - fault = Reset_Fault; - xc->regs.pc = ipr[TheISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault]; - xc->regs.npc = xc->regs.pc + sizeof(MachInst); #else xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0); - fault = No_Fault; #endif // !FULL_SYSTEM icacheInterface = icache_interface; @@ -524,8 +515,10 @@ SimpleCPU::tick() { traceData = NULL; + Fault fault = No_Fault; + #ifdef FULL_SYSTEM - if (fault == No_Fault && AlphaISA::check_interrupts && + if (AlphaISA::check_interrupts && xc->cpu->check_interrupts() && !PC_PAL(xc->regs.pc) && status() != IcacheMissComplete) { diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 60c038163..9e2c7fd06 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -154,9 +154,6 @@ class SimpleCPU : public BaseCPU // current instruction MachInst inst; - // current fault status - Fault fault; - // Refcounted pointer to the one memory request. MemReqPtr memReq; |