Merge zizzer:/bk/newmem

into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : ef75b46b9c1c267c84e6bb2b2234d46c4edcda16

28 files changed, 223 insertions, 289 deletions

diff --git a/SConscript b/SConscript
index 3693435b6..dd2df3703 100644
--- a/SConscript
+++ b/SConscript
@@ -188,6 +188,7 @@ full_system_sources = Split('''
 	dev/disk_image.cc
 	dev/io_device.cc
 	dev/isa_fake.cc
+	dev/pciconfigall.cc
 	dev/platform.cc
         dev/simconsole.cc
 	dev/simple_disk.cc
@@ -221,7 +222,6 @@ full_system_sources = Split('''
 #	dev/ide_ctrl.cc
 #	dev/ide_disk.cc
 #	dev/ns_gige.cc
-#	dev/pciconfigall.cc
 #	dev/pcidev.cc
 #	dev/pcifake.cc
 #	dev/pktfifo.cc
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 261ed8302..6fbf9d077 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -155,13 +155,8 @@ SimpleCPU::CpuPort::recvRetry()
 }
 
 SimpleCPU::SimpleCPU(Params *p)
-#if !FULL_SYSTEM
     : BaseCPU(p), mem(p->mem), icachePort(this),
       dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
-#else
-    : BaseCPU(p), icachePort(this), dcachePort(this),
-      tickEvent(this, p->width), cpuXC(NULL)
-#endif
 {
     _status = Idle;
 
@@ -1133,6 +1128,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     Param<Counter> max_insts_all_threads;
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
+    SimObjectParam<MemObject *> mem;
 
 #if FULL_SYSTEM
     SimObjectParam<AlphaITB *> itb;
@@ -1141,7 +1137,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     Param<int> cpu_id;
     Param<Tick> profile;
 #else
-    SimObjectParam<MemObject *> mem;
     SimObjectParam<Process *> workload;
 #endif // FULL_SYSTEM
 
@@ -1164,6 +1159,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
                "terminate when any thread reaches this load count"),
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
+    INIT_PARAM(mem, "memory"),
 
 #if FULL_SYSTEM
     INIT_PARAM(itb, "Instruction TLB"),
@@ -1172,7 +1168,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
     INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(profile, ""),
 #else
-    INIT_PARAM(mem, "memory"),
     INIT_PARAM(workload, "processes to run"),
 #endif // FULL_SYSTEM
 
@@ -1199,6 +1194,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
     params->functionTrace = function_trace;
     params->functionTraceStart = function_trace_start;
     params->width = width;
+    params->mem = mem;
 
 #if FULL_SYSTEM
     params->itb = itb;
@@ -1207,7 +1203,6 @@ CREATE_SIM_OBJECT(SimpleCPU)
     params->cpu_id = cpu_id;
     params->profile = profile;
 #else
-    params->mem = mem;
     params->process = workload;
 #endif
 
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 11137b6e6..0dbe7abfa 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -178,11 +178,11 @@ class SimpleCPU : public BaseCPU
     struct Params : public BaseCPU::Params
     {
         int width;
+        MemObject *mem;
 #if FULL_SYSTEM
         AlphaITB *itb;
         AlphaDTB *dtb;
 #else
-        MemObject *mem;
         Process *process;
 #endif
     };
diff --git a/dev/baddev.cc b/dev/baddev.cc
index f15c1d953..dcabdbe0a 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -35,13 +35,9 @@
 #include <vector>
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
 #include "dev/baddev.hh"
 #include "dev/platform.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
+#include "mem/port.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
@@ -49,7 +45,7 @@ using namespace std;
 using namespace TheISA;
 
 BadDevice::BadDevice(Params *p)
-    : BasicPioDevice(p), devname(p->devic_ename)
+    : BasicPioDevice(p), devname(p->device_name)
 {
     pioSize = 0xf;
 }
@@ -70,7 +66,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
 
     Param<string> devicename;
     Param<Addr> pio_addr;
-    SimObjectParam<AlphaSystem *> system;
+    SimObjectParam<System *> system;
     SimObjectParam<Platform *> platform;
     Param<Tick> pio_latency;
 
@@ -94,7 +90,7 @@ CREATE_SIM_OBJECT(BadDevice)
     p->pio_addr = pio_addr;
     p->pio_delay = pio_latency;
     p->system = system;
-    p->devicename = devicename;
+    p->device_name = devicename;
     return new BadDevice(p);
 }
 
diff --git a/dev/io_device.cc b/dev/io_device.cc
index 478c9c66e..a2e5a8a0d 100644
--- a/dev/io_device.cc
+++ b/dev/io_device.cc
@@ -88,6 +88,7 @@ PioDevice::~PioDevice()
         delete pioPort;
 }
 
+void
 PioDevice::init()
 {
     if (!pioPort)
diff --git a/dev/io_device.hh b/dev/io_device.hh
index 1e9a49899..5379a664c 100644
--- a/dev/io_device.hh
+++ b/dev/io_device.hh
@@ -30,7 +30,7 @@
 #define __DEV_IO_DEVICE_HH__
 
 #include "base/chunk_generator.hh"
-#include "mem/port.hh"
+#include "mem/mem_object.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 
@@ -172,7 +172,7 @@ class DmaPort : public Port
  * bother.
  */
 
-class PioDevice : public SimObject
+class PioDevice : public MemObject
 {
   protected:
 
@@ -224,7 +224,8 @@ class PioDevice : public SimObject
     const Params *params() const { return _params; }
 
     PioDevice(Params *p)
-              : SimObject(params()->name), platform(p->platform), _params(p)
+              : MemObject(p->name),  platform(p->platform), pioPort(NULL),
+                _params(p)
               {}
 
     virtual ~PioDevice();
@@ -272,7 +273,7 @@ class BasicPioDevice : public PioDevice
     /** return the address ranges that this device responds to.
      * @params range_list range list to populate with ranges
      */
-    addressRanges(AddrRangeList &range_list);
+    void addressRanges(AddrRangeList &range_list);
 
 };
 
diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc
index 7b6a01833..1ed355499 100644
--- a/dev/isa_fake.cc
+++ b/dev/isa_fake.cc
@@ -34,14 +34,9 @@
 #include <string>
 #include <vector>
 
-#include "arch/alpha/ev5.hh"
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
-#include "dev/tsunami_fake.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
+#include "dev/isa_fake.hh"
+#include "mem/packet.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
@@ -60,7 +55,6 @@ IsaFake::read(Packet &pkt)
     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
 
     pkt.time = curTick + pioDelay;
-    Addr daddr = pkt.addr - pioAddr;
 
     DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt.addr, pkt.size);
 
@@ -69,7 +63,7 @@ IsaFake::read(Packet &pkt)
     uint32_t *data32;
     uint64_t *data64;
 
-    switch (req->size) {
+    switch (pkt.size) {
       case sizeof(uint64_t):
          if (!pkt.data) {
              data64 = new uint64_t;
@@ -84,7 +78,7 @@ IsaFake::read(Packet &pkt)
              data32 = new uint32_t;
              pkt.data = (uint8_t*)data32;
          } else {
-             data32 = (uint64_t*)pkt.data;
+             data32 = (uint32_t*)pkt.data;
          }
          *data32 = 0xFFFFFFFF;
          break;
@@ -93,7 +87,7 @@ IsaFake::read(Packet &pkt)
              data16 = new uint16_t;
              pkt.data = (uint8_t*)data16;
          } else {
-             data16 = (uint64_t*)pkt.data;
+             data16 = (uint16_t*)pkt.data;
          }
          *data16 = 0xFFFF;
          break;
@@ -113,7 +107,7 @@ IsaFake::read(Packet &pkt)
     return pioDelay;
 }
 
-Fault
+Tick
 IsaFake::write(Packet &pkt)
 {
     pkt.time = curTick + pioDelay;
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index 1a138fb39..86a505b9a 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -35,34 +35,25 @@
 #include <vector>
 #include <bitset>
 
-#include "arch/alpha/ev5.hh"
 #include "base/trace.hh"
 #include "dev/pciconfigall.hh"
-#include "dev/pcidev.hh"
+//#include "dev/pcidev.hh"
 #include "dev/pcireg.h"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
+#include "dev/platform.hh"
+#include "mem/packet.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
-using namespace TheISA;
 
-PciConfigAll::PciConfigAll(const string &name,
-                           Addr a, MemoryController *mmu,
-                           HierParams *hier, Bus *pio_bus, Tick pio_latency)
-    : PioDevice(name, NULL), addr(a)
+PciConfigAll::PciConfigAll(Params *p)
+    : BasicPioDevice(p)
 {
-    mmu->add_child(this, RangeSize(addr, size));
+    pioSize = 0xffffff;
 
-    if (pio_bus) {
-        pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
-                                      &PciConfigAll::cacheAccess);
-        pioInterface->addAddrRange(RangeSize(addr, size));
-        pioLatency = pio_latency * pio_bus->clockRate;
-    }
+    // Set backpointer for pci config. Really the config stuff should be able to
+    // automagically do this
+    p->platform->pciconfig = this;
 
     // Make all the pointers to devices null
     for(int x=0; x < MAX_PCI_DEV; x++)
@@ -77,7 +68,7 @@ PciConfigAll::PciConfigAll(const string &name,
 void
 PciConfigAll::startup()
 {
-    bitset<256> intLines;
+/*    bitset<256> intLines;
     PciDev *tempDev;
     uint8_t intline;
 
@@ -94,79 +85,109 @@ PciConfigAll::startup()
            } // devices != NULL
         } // PCI_FUNC
     } // PCI_DEV
-
+  */
 }
 
-Fault
-PciConfigAll::read(MemReqPtr &req, uint8_t *data)
+Tick
+PciConfigAll::read(Packet &pkt)
 {
+    assert(pkt.result == Unknown);
+    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
 
-    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
-
-    DPRINTF(PciConfigAll, "read  va=%#x da=%#x size=%d\n",
-            req->vaddr, daddr, req->size);
-
+    Addr daddr = pkt.addr - pioAddr;
     int device = (daddr >> 11) & 0x1F;
     int func = (daddr >> 8) & 0x7;
-    int reg = daddr & 0xFF;
-
-    if (devices[device][func] == NULL) {
-        switch (req->size) {
-           // case sizeof(uint64_t):
-           //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
-           //     return NoFault;
-            case sizeof(uint32_t):
-                *(uint32_t*)data = 0xFFFFFFFF;
-                return NoFault;
-            case sizeof(uint16_t):
-                *(uint16_t*)data = 0xFFFF;
-                return NoFault;
-            case sizeof(uint8_t):
-                *(uint8_t*)data = 0xFF;
-                return NoFault;
-            default:
-                panic("invalid access size(?) for PCI configspace!\n");
-        }
-    } else {
-        switch (req->size) {
-            case sizeof(uint32_t):
-            case sizeof(uint16_t):
-            case sizeof(uint8_t):
-                devices[device][func]->readConfig(reg, req->size, data);
-                return NoFault;
-            default:
-                panic("invalid access size(?) for PCI configspace!\n");
-        }
+    //int reg = daddr & 0xFF;
+
+    pkt.time = curTick + pioDelay;
+
+    DPRINTF(PciConfigAll, "read  va=%#x da=%#x size=%d\n", pkt.addr, daddr,
+            pkt.size);
+
+    uint8_t *data8;
+    uint16_t *data16;
+    uint32_t *data32;
+
+    switch (pkt.size) {
+/*      case sizeof(uint64_t):
+         if (!pkt.data) {
+             data64 = new uint64_t;
+             pkt.data = (uint8_t*)data64;
+         } else {
+             data64 = (uint64_t*)pkt.data;
+         }
+         if (devices[device][func] == NULL)
+             *data64 = 0xFFFFFFFFFFFFFFFFULL;
+         else
+             devices[device][func]->readConfig(reg, req.size, data64);
+         break;*/
+      case sizeof(uint32_t):
+         if (!pkt.data) {
+             data32 = new uint32_t;
+             pkt.data = (uint8_t*)data32;
+         } else {
+             data32 = (uint32_t*)pkt.data;
+         }
+         if (devices[device][func] == NULL)
+             *data32 = 0xFFFFFFFF;
+         else
+             ;//devices[device][func]->readConfig(reg, req.size, data32);
+         break;
+      case sizeof(uint16_t):
+         if (!pkt.data) {
+             data16 = new uint16_t;
+             pkt.data = (uint8_t*)data16;
+         } else {
+             data16 = (uint16_t*)pkt.data;
+         }
+         if (devices[device][func] == NULL)
+             *data16 = 0xFFFF;
+         else
+             ;//devices[device][func]->readConfig(reg, req.size, data16);
+         break;
+      case sizeof(uint8_t):
+         if (!pkt.data) {
+             data8 = new uint8_t;
+             pkt.data = data8;
+         } else {
+             data8 = (uint8_t*)pkt.data;
+         }
+         if (devices[device][func] == NULL)
+             *data8 = 0xFF;
+         else
+             ;//devices[device][func]->readConfig(reg, req.size, data8);
+         break;
+      default:
+        panic("invalid access size(?) for PCI configspace!\n");
     }
-
-    DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
-             daddr, req->size);
-
-    return NoFault;
+    pkt.result = Success;
+    return pioDelay;
 }
 
-Fault
-PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
+Tick
+PciConfigAll::write(Packet &pkt)
 {
-    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
+    pkt.time = curTick + pioDelay;
+
+    assert(pkt.result == Unknown);
+    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
+    assert(pkt.size == sizeof(uint8_t) || pkt.size == sizeof(uint16_t) ||
+            pkt.size == sizeof(uint32_t));
+    Addr daddr = pkt.addr - pioAddr;
 
     int device = (daddr >> 11) & 0x1F;
     int func = (daddr >> 8) & 0x7;
-    int reg = daddr & 0xFF;
+//    int reg = daddr & 0xFF;
 
     if (devices[device][func] == NULL)
         panic("Attempting to write to config space on non-existant device\n");
-    else if (req->size != sizeof(uint8_t) &&
-             req->size != sizeof(uint16_t) &&
-             req->size != sizeof(uint32_t))
-        panic("invalid access size(?) for PCI configspace!\n");
 
     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
-            req->vaddr, req->size, *(uint32_t*)data);
+            pkt.addr, pkt.size, *(uint32_t*)pkt.data);
 
-    devices[device][func]->writeConfig(reg, req->size, data);
+//    devices[device][func]->writeConfig(reg, req->size, data);
 
-    return NoFault;
+    return pioDelay;
 }
 
 void
@@ -189,40 +210,34 @@ PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
      */
 }
 
-Tick
-PciConfigAll::cacheAccess(MemReqPtr &req)
-{
-    return curTick + pioLatency;
-}
-
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 
-    SimObjectParam<MemoryController *> mmu;
-    Param<Addr> addr;
-    Param<Addr> mask;
-    SimObjectParam<Bus*> pio_bus;
+    Param<Addr> pio_addr;
     Param<Tick> pio_latency;
-    SimObjectParam<HierParams *> hier;
+    SimObjectParam<Platform *> platform;
+    SimObjectParam<System *> system;
 
 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 
-    INIT_PARAM(mmu, "Memory Controller"),
-    INIT_PARAM(addr, "Device Address"),
-    INIT_PARAM(mask, "Address Mask"),
-    INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
+    INIT_PARAM(pio_addr, "Device Address"),
+    INIT_PARAM(pio_latency, "Programmed IO latency"),
+    INIT_PARAM(platform, "platform"),
+    INIT_PARAM(system, "system object")
 
 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 
 CREATE_SIM_OBJECT(PciConfigAll)
 {
-    return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus,
-                            pio_latency);
+    BasicPioDevice::Params *p = new BasicPioDevice::Params;
+    p->pio_addr = pio_addr;
+    p->pio_delay = pio_latency;
+    p->platform = platform;
+    p->system = system;
+    return new PciConfigAll(p);
 }
 
 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh
index c6a0241d8..b2034594c 100644
--- a/dev/pciconfigall.hh
+++ b/dev/pciconfigall.hh
@@ -43,7 +43,6 @@ static const uint32_t MAX_PCI_DEV = 32;
 static const uint32_t MAX_PCI_FUNC = 8;
 
 class PciDev;
-class MemoryController;
 
 /**
  * PCI Config Space
@@ -52,10 +51,9 @@ class MemoryController;
  * space and passes the requests on to TsunamiPCIDev devices as
  * appropriate.
  */
-class PciConfigAll : public PioDevice
+class PciConfigAll : public BasicPioDevice
 {
   private:
-    Addr addr;
     static const Addr size = 0xffffff;
 
     /**
@@ -67,15 +65,9 @@ class PciConfigAll : public PioDevice
   public:
     /**
      * Constructor for PCIConfigAll
-     * @param name name of the object
-     * @param a base address of the write
-     * @param mmu the memory controller
-     * @param hier object to store parameters universal the device hierarchy
-     * @param bus The bus that this device is attached to
+     * @param p parameters structure
      */
-    PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
-                 HierParams *hier, Bus *pio_bus, Tick pio_latency);
-
+    PciConfigAll(Params *p);
 
     /**
      * Check if a device exists.
@@ -99,11 +91,10 @@ class PciConfigAll : public PioDevice
      * Read something in PCI config space. If the device does not exist
      * -1 is returned, if the device does exist its PciDev::ReadConfig (or the
      * virtual function that overrides) it is called.
-     * @param req Contains the address of the field to read.
-     * @param data Return the field read.
-     * @return The fault condition of the access.
+     * @param pkt Contains the address of the field to read.
+     * @return Amount of time to do the read
      */
-    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Tick read(Packet &pkt);
 
     /**
      * Write to PCI config spcae. If the device does not exit the simulator
@@ -114,7 +105,7 @@ class PciConfigAll : public PioDevice
      * @return The fault condition of the access.
      */
 
-    virtual Fault write(MemReqPtr &req, const uint8_t *data);
+    virtual Tick write(Packet &pkt);
 
     /**
      * Start up function to check if more than one person is using an interrupt line
@@ -134,14 +125,6 @@ class PciConfigAll : public PioDevice
      * @param section The section name of this object
      */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-    /**
-     * Return how long this access will take.
-     * @param req the memory request to calcuate
-     * @return Tick when the request is done
-     */
-    Tick cacheAccess(MemReqPtr &req);
-
 };
 
 #endif // __PCICONFIGALL_HH__
diff --git a/dev/platform.cc b/dev/platform.cc
index 5b667b12c..9d10e0828 100644
--- a/dev/platform.cc
+++ b/dev/platform.cc
@@ -33,8 +33,8 @@
 using namespace std;
 using namespace TheISA;
 
-Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci)
-    : SimObject(name), intrctrl(intctrl), pciconfig(pci)
+Platform::Platform(const string &name, IntrControl *intctrl)
+    : SimObject(name), intrctrl(intctrl)
 {
 }
 
diff --git a/dev/platform.hh b/dev/platform.hh
index 2c37048d4..f149ca2fb 100644
--- a/dev/platform.hh
+++ b/dev/platform.hh
@@ -59,8 +59,9 @@ class Platform : public SimObject
     System *system;
 
   public:
-    Platform(const std::string &name, IntrControl *intctrl, PciConfigAll *pci);
+    Platform(const std::string &name, IntrControl *intctrl);
     virtual ~Platform();
+    virtual void init() { if (pciconfig == NULL) panic("PCI Config not set"); }
     virtual void postConsoleInt() = 0;
     virtual void clearConsoleInt() = 0;
     virtual Tick intrFrequency() = 0;
diff --git a/dev/tsunami.cc b/dev/tsunami.cc
index 58fc7434e..ed011531d 100644
--- a/dev/tsunami.cc
+++ b/dev/tsunami.cc
@@ -36,12 +36,10 @@
 
 #include "cpu/intr_control.hh"
 #include "dev/simconsole.hh"
-#include "dev/ide_ctrl.hh"
 #include "dev/tsunami_cchip.hh"
 #include "dev/tsunami_pchip.hh"
 #include "dev/tsunami_io.hh"
 #include "dev/tsunami.hh"
-#include "dev/pciconfigall.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
@@ -49,9 +47,8 @@ using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
-                 PciConfigAll *pci)
-    : Platform(name, ic, pci), system(s)
+Tsunami::Tsunami(const string &name, System *s, IntrControl *ic)
+    : Platform(name, ic), system(s)
 {
     // set the back pointer from the system to myself
     system->platform = this;
@@ -112,21 +109,19 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
 
     SimObjectParam<System *> system;
     SimObjectParam<IntrControl *> intrctrl;
-    SimObjectParam<PciConfigAll *> pciconfig;
 
 END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
 
     INIT_PARAM(system, "system"),
-    INIT_PARAM(intrctrl, "interrupt controller"),
-    INIT_PARAM(pciconfig, "PCI configuration")
+    INIT_PARAM(intrctrl, "interrupt controller")
 
 END_INIT_SIM_OBJECT_PARAMS(Tsunami)
 
 CREATE_SIM_OBJECT(Tsunami)
 {
-    return new Tsunami(getInstanceName(), system, intrctrl, pciconfig);
+    return new Tsunami(getInstanceName(), system, intrctrl);
 }
 
 REGISTER_SIM_OBJECT("Tsunami", Tsunami)
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index 7fd91d5b2..668c82674 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -38,12 +38,9 @@
 #include "dev/platform.hh"
 
 class IdeController;
-class TlaserClock;
-class NSGigE;
 class TsunamiCChip;
 class TsunamiPChip;
 class TsunamiIO;
-class PciConfigAll;
 class System;
 
 /**
@@ -86,8 +83,7 @@ class Tsunami : public Platform
      * @param name name of the object
      * @param intrctrl pointer to the interrupt controller
      */
-    Tsunami(const std::string &name, System *s, IntrControl *intctrl,
-            PciConfigAll *pci);
+    Tsunami(const std::string &name, System *s, IntrControl *intctrl);
 
     /**
      * Return the interrupting frequency to AlphaAccess
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 645b64d14..b15f6fefb 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -71,16 +71,15 @@ TsunamiCChip::TsunamiCChip(Params *p)
 Tick
 TsunamiCChip::read(Packet &pkt)
 {
-    DPRINTF(Tsunami, "read  va=%#x size=%d\n", req->vaddr, req->size);
+    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt.addr, pkt.size);
 
     assert(pkt.result == Unknown);
     assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
 
     pkt.time = curTick + pioDelay;
-    Addr regnum = (req->paddr - pioAddr) >> 6;
-    Addr daddr = (req->paddr - pioAddr);
+    Addr regnum = (pkt.addr - pioAddr) >> 6;
+    Addr daddr = (pkt.addr - pioAddr);
 
-    uint32_t *data32;
     uint64_t *data64;
 
     switch (pkt.size) {
@@ -113,7 +112,7 @@ TsunamiCChip::read(Packet &pkt)
                    break;
               case TSDEV_CC_MISC:
                   *data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF |
-                                     (pkt.req->cpuId & 0x3);
+                                     (pkt.req->getCpuNum() & 0x3);
                   break;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1:
@@ -181,7 +180,7 @@ TsunamiCChip::read(Packet &pkt)
         panic("invalid access size(?) for tsunami register!\n");
     }
     DPRINTFN("Tsunami CChip: read  regnum=%#x size=%d data=%lld\n", regnum,
-            req->size, *data);
+            pkt.size, *data64);
 
     pkt.result = Success;
     return pioDelay;
@@ -201,7 +200,7 @@ TsunamiCChip::write(Packet &pkt)
     uint64_t val = *(uint64_t *)pkt.data;
     assert(pkt.size == sizeof(uint64_t));
 
-    DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", req->addr, val);
+    DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt.addr, val);
 
     bool supportedWrite = false;
 
@@ -289,7 +288,6 @@ TsunamiCChip::write(Packet &pkt)
             case TSDEV_CC_AAR2:
             case TSDEV_CC_AAR3:
                 panic("TSDEV_CC_AARx write not implemeted\n");
-                return NoFault;
             case TSDEV_CC_DIM0:
             case TSDEV_CC_DIM1:
             case TSDEV_CC_DIM2:
@@ -508,12 +506,6 @@ TsunamiCChip::clearDRIR(uint32_t interrupt)
         DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
 }
 
-Tick
-TsunamiCChip::cacheAccess(MemReqPtr &req)
-{
-    return curTick + pioLatency;
-}
-
 
 void
 TsunamiCChip::serialize(std::ostream &os)
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 5b73230bf..ebf3492ac 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -36,16 +36,16 @@
 #include <string>
 #include <vector>
 
-#include "arch/alpha/ev5.hh"
 #include "base/trace.hh"
-#include "dev/tsunami_io.hh"
-#include "dev/tsunami.hh"
 #include "dev/pitreg.h"
-#include "mem/bus/port.hh"
-#include "sim/builder.hh"
+#include "dev/rtcreg.h"
 #include "dev/tsunami_cchip.hh"
+#include "dev/tsunami.hh"
+#include "dev/tsunami_io.hh"
 #include "dev/tsunamireg.h"
-#include "dev/rtcreg.h"
+#include "mem/port.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
@@ -79,7 +79,7 @@ TsunamiIO::RTC::set_time(time_t t)
 void
 TsunamiIO::RTC::writeAddr(const uint8_t data)
 {
-    if (*data <= RTC_STAT_REGD)
+    if (data <= RTC_STAT_REGD)
         addr = data;
     else
         panic("RTC addresses over 0xD are not implemented.\n");
@@ -95,13 +95,13 @@ TsunamiIO::RTC::writeData(const uint8_t data)
           case RTC_STAT_REGA:
             if (data != (RTCA_32768HZ | RTCA_1024HZ))
                 panic("Unimplemented RTC register A value write!\n");
-            stat_regA = *data;
+            stat_regA = data;
             break;
           case RTC_STAT_REGB:
             if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
                 panic("Write to RTC reg B bits that are not implemented!\n");
 
-            if (*data & RTCB_PRDC_IE) {
+            if (data & RTCB_PRDC_IE) {
                 if (!event.scheduled())
                     event.scheduleIntr();
             } else {
@@ -214,7 +214,7 @@ TsunamiIO::PITimer::writeControl(const uint8_t data)
     if (sel == PIT_READ_BACK)
        panic("PITimer Read-Back Command is not implemented.\n");
 
-    rw = GET_CTRL_RW(*data);
+    rw = GET_CTRL_RW(data);
 
     if (rw == PIT_RW_LATCH_COMMAND)
         counter[sel]->latchCount();
@@ -416,7 +416,7 @@ TsunamiIO::PITimer::Counter::CounterEvent::description()
 
 TsunamiIO::TsunamiIO(Params *p)
     : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
-      rtc(name + ".rtc", p->tsunami, p->frequency)
+      rtc(p->name + ".rtc", p->tsunami, p->frequency)
 {
     pioSize = 0xff;
 
@@ -424,7 +424,7 @@ TsunamiIO::TsunamiIO(Params *p)
     tsunami->io = this;
 
     timerData = 0;
-    rtc.set_time(p->init_time == 0 ? time(NULL) : init_time);
+    rtc.set_time(p->init_time == 0 ? time(NULL) : p->init_time);
     picr = 0;
     picInterrupting = false;
 }
@@ -435,7 +435,7 @@ TsunamiIO::frequency() const
     return Clock::Frequency / params()->frequency;
 }
 
-Fault
+Tick
 TsunamiIO::read(Packet &pkt)
 {
     assert(pkt.result == Unknown);
@@ -478,10 +478,10 @@ TsunamiIO::read(Packet &pkt)
               break;
           case TSDEV_TMR0_DATA:
             pitimer.counter0.read(data8);
-            return NoFault;
+            break;
           case TSDEV_TMR1_DATA:
             pitimer.counter1.read(data8);
-            return NoFault;
+            break;
           case TSDEV_TMR2_DATA:
             pitimer.counter2.read(data8);
             break;
@@ -502,15 +502,15 @@ TsunamiIO::read(Packet &pkt)
             data64 = new uint64_t;
             pkt.data = (uint8_t*)data64;
         } else
-            data8 = (uint64_t*)pkt.data;
+            data64 = (uint64_t*)pkt.data;
 
         if (daddr == TSDEV_PIC1_ISR)
-            data64 = (uint64_t)picr;
+            *data64 = picr;
         else
            panic("I/O Read - invalid addr - va %#x size %d\n",
-                   req.addr, req.size);
+                   pkt.addr, pkt.size);
     } else {
-       panic("I/O Read - invalid size - va %#x size %d\n", req.addr, req.size);
+       panic("I/O Read - invalid size - va %#x size %d\n", pkt.addr, pkt.size);
     }
     pkt.result = Success;
     return pioDelay;
@@ -531,7 +531,7 @@ TsunamiIO::write(Packet &pkt)
 #endif
 
     DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
-            req->vaddr, req->size, req->vaddr & 0xfff, dt64);
+            pkt.addr, pkt.size, pkt.addr & 0xfff, dt64);
 
     assert(pkt.size == sizeof(uint8_t));
 
@@ -671,10 +671,9 @@ END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
 
-    INIT_PARAM(frequency, "clock interrupt frequency"),
     INIT_PARAM(pio_addr, "Device Address"),
     INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(pio_size, "Size of address range"),
+    INIT_PARAM(frequency, "clock interrupt frequency"),
     INIT_PARAM(platform, "platform"),
     INIT_PARAM(system, "system object"),
     INIT_PARAM(time, "System time to use (0 for actual time"),
diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh
index defb850ce..c37f3aa16 100644
--- a/dev/tsunami_io.hh
+++ b/dev/tsunami_io.hh
@@ -42,7 +42,7 @@
  * Tsunami I/O device is a catch all for all the south bridge stuff we care
  * to implement.
  */
-class TsunamiIO : public PioDevice
+class TsunamiIO : public BasicPioDevice
 {
   private:
     struct tm tm;
@@ -318,8 +318,8 @@ class TsunamiIO : public PioDevice
      */
     TsunamiIO(Params *p);
 
-    virtual Fault read(Packet &pkt);
-    virtual Fault write(Packet &pkt);
+    virtual Tick read(Packet &pkt);
+    virtual Tick write(Packet &pkt);
 
     /**
      * Post an PIC interrupt to the CPU via the CChip
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index 239d12ee9..2f06cf493 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -34,16 +34,11 @@
 #include <string>
 #include <vector>
 
-#include "arch/alpha/ev5.hh"
 #include "base/trace.hh"
 #include "dev/tsunami_pchip.hh"
 #include "dev/tsunamireg.h"
 #include "dev/tsunami.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
+#include "mem/packet.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
@@ -52,7 +47,7 @@ using namespace std;
 using namespace TheISA;
 
 TsunamiPChip::TsunamiPChip(Params *p)
-: BasicPioDevice(p),
+: BasicPioDevice(p)
 {
     pioSize = 0xfff;
 
@@ -122,7 +117,7 @@ TsunamiPChip::read(Packet &pkt)
       case TSDEV_PC_TBA2:
             *data64 = tba[2];
             break;
-      case Tbreak;
+      case TSDEV_PC_TBA3:
             *data64 = tba[3];
             break;
       case TSDEV_PC_PCTL:
@@ -157,7 +152,7 @@ TsunamiPChip::read(Packet &pkt)
 
 }
 
-Fault
+Tick
 TsunamiPChip::write(Packet &pkt)
 {
     pkt.time = curTick + pioDelay;
@@ -166,7 +161,7 @@ TsunamiPChip::write(Packet &pkt)
     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
     Addr daddr = pkt.addr - pioAddr;
 
-    uint64_t val = *(uint64_t *)pkt.data;
+    uint64_t data64 = *(uint64_t *)pkt.data;
     assert(pkt.size == sizeof(uint64_t));
 
     DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size);
@@ -295,7 +290,7 @@ TsunamiPChip::translatePciToDma(Addr busAddr)
                     baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
                     pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
 
-                    pioPort->readBlob(&pteEntry, pteAddr, sizeof(uint64_t));
+                    pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
 
                     dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
 
@@ -332,11 +327,6 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_ARRAY(tba, 4);
 }
 
-Tick
-TsunamiPChip::cacheAccess(MemReqPtr &req)
-{
-    return curTick + pioLatency;
-}
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
 
diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh
index 796d38503..2f3e8f078 100644
--- a/dev/tsunami_pchip.hh
+++ b/dev/tsunami_pchip.hh
@@ -78,8 +78,8 @@ class TsunamiPChip : public BasicPioDevice
      */
     Addr translatePciToDma(Addr busAddr);
 
-    virtual Fault read(Packet &pkt);
-    virtual Fault write(Packet &pkt);
+    virtual Tick read(Packet &pkt);
+    virtual Tick write(Packet &pkt);
 
     /**
      * Serialize this object to the given output stream.
diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index bbb42c065..7c8899180 100644
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -336,7 +336,7 @@ Uart8250::unserialize(Checkpoint *cp, const std::string &section)
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 
-    Param<Addr> addr;
+    Param<Addr> pio_addr;
     Param<Tick> pio_latency;
     SimObjectParam<Platform *> platform;
     SimObjectParam<SimConsole *> sim_console;
@@ -346,7 +346,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
 
-    INIT_PARAM(addr, "Device Address"),
+    INIT_PARAM(pio_addr, "Device Address"),
     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
     INIT_PARAM(platform, "platform"),
     INIT_PARAM(sim_console, "The Simulator Console"),
@@ -358,7 +358,7 @@ CREATE_SIM_OBJECT(Uart8250)
 {
     Uart8250::Params *p = new Uart8250::Params;
     p->name = getInstanceName();
-    p->pio_addr = addr;
+    p->pio_addr = pio_addr;
     p->pio_delay = pio_latency;
     p->platform = platform;
     p->cons = sim_console;
diff --git a/python/m5/objects/AlphaConsole.py b/python/m5/objects/AlphaConsole.py
index f8f034682..68e6089ab 100644
--- a/python/m5/objects/AlphaConsole.py
+++ b/python/m5/objects/AlphaConsole.py
@@ -1,9 +1,9 @@
 from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
 
-class AlphaConsole(PioDevice):
+class AlphaConsole(BasicPioDevice):
     type = 'AlphaConsole'
     cpu = Param.BaseCPU(Parent.any, "Processor")
     disk = Param.SimpleDisk("Simple Disk")
     sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
-    system = Param.System(Parent.any, "system object")
+    system = Param.AlphaSystem(Parent.any, "system object")
diff --git a/python/m5/objects/BadDevice.py b/python/m5/objects/BadDevice.py
index 3fba4637d..9cb9a8f03 100644
--- a/python/m5/objects/BadDevice.py
+++ b/python/m5/objects/BadDevice.py
@@ -1,6 +1,6 @@
 from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
 
-class BadDevice(PioDevice):
+class BadDevice(BasicPioDevice):
     type = 'BadDevice'
     devicename = Param.String("Name of device to error on")
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index fccddb1ec..49cb2a8f3 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -2,6 +2,7 @@ from m5 import *
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
+    mem = Param.MemObject("memory")
 
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB("Data TLB")
@@ -9,7 +10,6 @@ class BaseCPU(SimObject):
         system = Param.System(Parent.any, "system object")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
-        mem = Param.MemObject("memory")
         workload = VectorParam.Process("processes to run")
 
     max_insts_all_threads = Param.Counter(0,
diff --git a/python/m5/objects/Device.py b/python/m5/objects/Device.py
index d7ca014a9..cda3b1824 100644
--- a/python/m5/objects/Device.py
+++ b/python/m5/objects/Device.py
@@ -1,35 +1,14 @@
 from m5 import *
-from FunctionalMemory import FunctionalMemory
+from MemObject import MemObject
 
-# This device exists only because there are some devices that I don't
-# want to have a Platform parameter because it would cause a cycle in
-# the C++ that cannot be easily solved.
-#
-# The real solution to this problem is to pass the ParamXXX structure
-# to the constructor, but with the express condition that SimObject
-# parameter values are not to be available at construction time.  If
-# some further configuration must be done, it must be done during the
-# initialization phase at which point all SimObject pointers will be
-# valid.
-class FooPioDevice(FunctionalMemory):
+class PioDevice(MemObject):
     type = 'PioDevice'
     abstract = True
-    addr = Param.Addr("Device Address")
-    mmu = Param.MemoryController(Parent.any, "Memory Controller")
-    pio_bus = Param.Bus(NULL, "Bus to attach to for PIO")
-    pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
+    platform = Param.Platform(Parent.any, "Platform this device is part of")
+    system = Param.System(Parent.any, "System this device is part of")
 
-class FooDmaDevice(FooPioDevice):
-    type = 'DmaDevice'
+class BasicPioDevice(PioDevice):
+    type = 'BasicPioDevice'
     abstract = True
-    dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
-
-class PioDevice(FooPioDevice):
-    type = 'PioDevice'
-    abstract = True
-    platform = Param.Platform(Parent.any, "Platform")
-
-class DmaDevice(PioDevice):
-    type = 'DmaDevice'
-    abstract = True
-    dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
+    pio_addr = Param.Addr("Device Address")
+    pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py
index 4124d0b92..f2ccce09f 100644
--- a/python/m5/objects/Pci.py
+++ b/python/m5/objects/Pci.py
@@ -1,5 +1,6 @@
 from m5 import *
-from Device import FooPioDevice, DmaDevice
+from Device import BasicPioDevice
+#, DmaDevice
 
 class PciConfigData(SimObject):
     type = 'PciConfigData'
@@ -38,18 +39,18 @@ class PciConfigData(SimObject):
     MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
     MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
 
-class PciConfigAll(FooPioDevice):
+class PciConfigAll(BasicPioDevice):
     type = 'PciConfigAll'
 
-class PciDevice(DmaDevice):
-    type = 'PciDevice'
-    abstract = True
-    addr = 0xffffffffL
-    pci_bus = Param.Int("PCI bus")
-    pci_dev = Param.Int("PCI device number")
-    pci_func = Param.Int("PCI function code")
-    configdata = Param.PciConfigData(Parent.any, "PCI Config data")
-    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
-
-class PciFake(PciDevice):
-    type = 'PciFake'
+#class PciDevice(DmaDevice):
+#    type = 'PciDevice'
+#    abstract = True
+#    addr = 0xffffffffL
+#    pci_bus = Param.Int("PCI bus")
+#    pci_dev = Param.Int("PCI device number")
+#    pci_func = Param.Int("PCI function code")
+#    configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+#    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
+#
+#class PciFake(PciDevice):
+#    type = 'PciFake'
diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py
index b0aba1a7d..b69c969cb 100644
--- a/python/m5/objects/PhysicalMemory.py
+++ b/python/m5/objects/PhysicalMemory.py
@@ -5,5 +5,3 @@ class PhysicalMemory(Memory):
     type = 'PhysicalMemory'
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")
-    if build_env['FULL_SYSTEM']:
-        mmu = Param.MemoryController(Parent.any, "Memory Controller")
diff --git a/python/m5/objects/System.py b/python/m5/objects/System.py
index 2959c1d1a..65b621dff 100644
--- a/python/m5/objects/System.py
+++ b/python/m5/objects/System.py
@@ -6,7 +6,6 @@ class System(SimObject):
     if build_env['FULL_SYSTEM']:
         boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                              "boot processor frequency")
-        memctrl = Param.MemoryController(Parent.any, "memory controller")
         init_param = Param.UInt64(0, "numerical value to pass into simulator")
         bin = Param.Bool(False, "is this system binned")
         binned_fns = VectorParam.String([], "functions broken down and binned")
diff --git a/python/m5/objects/Tsunami.py b/python/m5/objects/Tsunami.py
index 5425f421f..27ea0bce8 100644
--- a/python/m5/objects/Tsunami.py
+++ b/python/m5/objects/Tsunami.py
@@ -1,27 +1,27 @@
 from m5 import *
-from Device import FooPioDevice
+from Device import BasicPioDevice
 from Platform import Platform
 
 class Tsunami(Platform):
     type = 'Tsunami'
-    pciconfig = Param.PciConfigAll("PCI configuration")
+#    pciconfig = Param.PciConfigAll("PCI configuration")
     system = Param.System(Parent.any, "system")
 
-class TsunamiCChip(FooPioDevice):
+class TsunamiCChip(BasicPioDevice):
     type = 'TsunamiCChip'
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
 
-class IsaFake(FooPioDevice):
+class IsaFake(BasicPioDevice):
     type = 'IsaFake'
-    size = Param.Addr("Size of address range")
+    pio_size = Param.Addr(0x8, "Size of address range")
 
-class TsunamiIO(FooPioDevice):
+class TsunamiIO(BasicPioDevice):
     type = 'TsunamiIO'
     time = Param.UInt64(1136073600,
         "System time to use (0 for actual time, default is 1/1/06)")
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
     frequency = Param.Frequency('1024Hz', "frequency of interrupts")
 
-class TsunamiPChip(FooPioDevice):
+class TsunamiPChip(BasicPioDevice):
     type = 'TsunamiPChip'
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
diff --git a/python/m5/objects/Uart.py b/python/m5/objects/Uart.py
index 6eda5cdb3..54754aeb9 100644
--- a/python/m5/objects/Uart.py
+++ b/python/m5/objects/Uart.py
@@ -1,11 +1,10 @@
 from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
 
-class Uart(PioDevice):
+class Uart(BasicPioDevice):
     type = 'Uart'
     abstract = True
-    console = Param.SimConsole(Parent.any, "The console")
-    size = Param.Addr(0x8, "Device size")
+    sim_console = Param.SimConsole(Parent.any, "The console")
 
 class Uart8250(Uart):
     type = 'Uart8250'