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| author | Alec Roelke <ar4jc@virginia.edu> | 2018-01-04 19:04:43 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2018-01-05 04:46:25 +0000 |
| commit | b001475a1ff5d4693f4d8b9063b3d602f7dd8043 (patch) | |
| tree | eeff8fd6b1b44bae8826b3ceabac1ba1961efe17 | |
| parent | 0d9f83789bada086ef0901ac30ec31954e905ede (diff) | |
| download | gem5-b001475a1ff5d4693f4d8b9063b3d602f7dd8043.tar.xz | |
arch-riscv: Correct syscall argument reg count
As per the discussion in patch #6904 and the Linux 4.15 kernel code for
RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0
through a6), with x17 (a7) being used for the system call number.
Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
Reviewed-on: https://gem5-review.googlesource.com/7081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
| -rw-r--r-- | src/arch/riscv/registers.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 01e385957..a61554c13 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -97,6 +97,10 @@ const std::vector<int> ReturnValueRegs = {10, 11}; const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; const int AMOTempReg = 32; +const int SyscallPseudoReturnReg = 10; +const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16}; +const int SyscallNumReg = 17; + const std::vector<std::string> IntRegNames = { "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", @@ -118,10 +122,6 @@ const std::vector<std::string> FloatRegNames = { "ft8", "ft9", "ft10", "ft11" }; -const int SyscallNumReg = 17; -const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13}; -const int SyscallPseudoReturnReg = 10; - enum MiscRegIndex { MISCREG_USTATUS = 0x000, MISCREG_UIE = 0x004, |