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| author | Kevin Lim <ktlim@umich.edu> | 2006-11-26 11:46:58 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-11-26 11:46:58 -0500 |
| commit | 07e525e8b78fba0ebaf5c50f32fbf30d17051891 (patch) | |
| tree | 22241e9d1b6bcf003128a1a9a9c3ae67eb3ff2d2 | |
| parent | 28f8318252a80e58fe77ea026d4b7b66146ad216 (diff) | |
| download | gem5-07e525e8b78fba0ebaf5c50f32fbf30d17051891.tar.xz | |
Include check for making sure caches are enabled.
--HG--
extra : convert_revision : e3902b065db524ebe5bf762e44a840133ccb8d75
| -rw-r--r-- | configs/common/Simulation.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 374ff3fc2..e037d0343 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -39,6 +39,9 @@ def setCPUClass(options): if options.timing: TmpClass = TimingSimpleCPU elif options.detailed: + if not options.caches: + print "O3 CPU must be used with caches" + sys.exit(1) TmpClass = DerivO3CPU else: TmpClass = AtomicSimpleCPU |