Merge gblack@m5.eecs.umich.edu:/bk/multiarch

into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348

102 files changed, 663 insertions, 463 deletions

diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc
index fb5e32e63..af4df7c30 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/alpha_linux_process.cc
@@ -52,6 +52,7 @@
 #include "base/trace.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 ///
 /// This class encapsulates the types, structures, constants,
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index 849063f59..b39a1ef26 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -42,6 +42,7 @@ class ExecContext;
 class AlphaTLB : public SimObject
 {
   protected:
+    typedef TheISA::Addr Addr;
     typedef std::multimap<Addr, int> PageTable;
     PageTable lookupTable;	// Quick lookup into page table
 
@@ -82,6 +83,7 @@ class AlphaTLB : public SimObject
 class AlphaITB : public AlphaTLB
 {
   protected:
+    typedef TheISA::Addr Addr;
     mutable Stats::Scalar<> hits;
     mutable Stats::Scalar<> misses;
     mutable Stats::Scalar<> acv;
diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/alpha_tru64_process.cc
index 5c24adad9..49e672203 100644
--- a/arch/alpha/alpha_tru64_process.cc
+++ b/arch/alpha/alpha_tru64_process.cc
@@ -55,6 +55,7 @@
 #include "sim/syscall_emul.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 typedef struct stat global_stat;
 typedef struct statfs global_statfs;
diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc
index a340a2053..4e8190cbc 100644
--- a/arch/alpha/arguments.cc
+++ b/arch/alpha/arguments.cc
@@ -31,6 +31,8 @@
 #include "cpu/exec_context.hh"
 #include "mem/functional/physical.hh"
 
+using namespace AlphaISA;
+
 AlphaArguments::Data::~Data()
 {
     while (!data.empty()) {
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 5173b364f..7c8465cfb 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -30,9 +30,13 @@
 #define __ARCH_ALPHA_EV5_HH__
 
 #include "config/alpha_tlaser.hh"
+#include "arch/alpha/isa_traits.hh"
 
 namespace EV5 {
 
+//It seems like a safe assumption EV5 only applies to alpha
+using namespace AlphaISA;
+
 #if ALPHA_TLASER
 const uint64_t AsnMask = ULL(0x7f);
 #else
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 2bb929a1e..8c281593a 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -34,15 +34,21 @@
 
 class AlphaFault : public Fault
 {
-public:
-        AlphaFault(char * newName, int newId, Addr newVect) : Fault(newName, newId), vect(newVect) {;}
-        TheISA::Addr vect;
+  protected:
+    typedef TheISA::Addr Addr;
+  public:
+    AlphaFault(char * newName, int newId, Addr newVect) :
+        Fault(newName, newId), vect(newVect)
+    {;}
+    Addr vect;
 };
 
 extern class ResetFaultType : public AlphaFault
 {
 public:
-        ResetFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+        ResetFaultType(char * newName, int newId, Addr newVect) :
+            AlphaFault(newName, newId, newVect)
+        {;}
 } * ResetFault;
 
 extern class ArithmeticFaultType : public AlphaFault
diff --git a/arch/alpha/isa/branch.isa b/arch/alpha/isa/branch.isa
index e9c790c53..cc6fd1a09 100644
--- a/arch/alpha/isa/branch.isa
+++ b/arch/alpha/isa/branch.isa
@@ -40,6 +40,8 @@ output header {{
     class PCDependentDisassembly : public AlphaStaticInst
     {
       protected:
+        typedef TheISA::Addr Addr;
+      protected:
         /// Cached program counter from last disassembly
         mutable Addr cachedPC;
         /// Cached symbol table pointer from last disassembly
@@ -64,6 +66,7 @@ output header {{
     class Branch : public PCDependentDisassembly
     {
       protected:
+        typedef TheISA::Addr Addr;
         /// Displacement to target address (signed).
         int32_t disp;
 
@@ -87,6 +90,7 @@ output header {{
     class Jump : public PCDependentDisassembly
     {
       protected:
+        typedef TheISA::Addr Addr;
 
         /// Displacement to target address (signed).
         int32_t disp;
@@ -205,8 +209,8 @@ output decoder {{
 
 def template JumpOrBranchDecode {{
     return (RA == 31)
-        ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
-        : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
+        ? (StaticInst *)new %(class_name)s(machInst)
+        : (StaticInst *)new %(class_name)sAndLink(machInst);
 }};
 
 def format CondBranch(code) {{
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index 42fb29404..862b2b95e 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -45,6 +45,8 @@ output decoder {{
 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
 
 #include <math.h>
+
+using namespace AlphaISA;
 }};
 
 output exec {{
@@ -58,6 +60,8 @@ output exec {{
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
+
+using namespace AlphaISA;
 }};
 
 ////////////////////////////////////////////////////////////////////
@@ -179,7 +183,7 @@ output header {{
     /**
      * Base class for all Alpha static instructions.
      */
-    class AlphaStaticInst : public StaticInst<AlphaISA>
+    class AlphaStaticInst : public StaticInst
     {
       protected:
 
@@ -196,7 +200,7 @@ output header {{
         /// Constructor.
         AlphaStaticInst(const char *mnem, MachInst _machInst,
                         OpClass __opClass)
-            : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
+            : StaticInst(mnem, _machInst, __opClass)
         {
         }
 
@@ -352,6 +356,17 @@ output header {{
 
         %(BasicExecDeclare)s
     };
+
+    /// Helper function for decoding nops.  Substitute Nop object
+    /// for original inst passed in as arg (and delete latter).
+    static inline
+    AlphaStaticInst *
+    makeNop(AlphaStaticInst *inst)
+    {
+        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+        delete inst;
+        return nop;
+    }
 }};
 
 output decoder {{
@@ -364,17 +379,6 @@ output decoder {{
         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 #endif
     }
-
-    /// Helper function for decoding nops.  Substitute Nop object
-    /// for original inst passed in as arg (and delete latter).
-    inline
-    AlphaStaticInst *
-    makeNop(AlphaStaticInst *inst)
-    {
-        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
-        delete inst;
-        return nop;
-    }
 }};
 
 output exec {{
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 0b79bc376..c72806263 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -37,14 +37,14 @@ output header {{
         /// Memory request flags.  See mem_req_base.hh.
         unsigned memAccessFlags;
         /// Pointer to EAComp object.
-        const StaticInstPtr<AlphaISA> eaCompPtr;
+        const StaticInstPtr eaCompPtr;
         /// Pointer to MemAcc object.
-        const StaticInstPtr<AlphaISA> memAccPtr;
+        const StaticInstPtr memAccPtr;
 
         /// Constructor
         Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
-               StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
-               StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+               StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+               StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : AlphaStaticInst(mnem, _machInst, __opClass),
               memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
         {
@@ -55,8 +55,8 @@ output header {{
 
       public:
 
-        const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
-        const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
+        const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
+        const StaticInstPtr &memAccInst() const { return memAccPtr; }
     };
 
     /**
@@ -71,8 +71,8 @@ output header {{
 
         /// Constructor.
         MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
-                     StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
-                     StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
               disp(MEMDISP)
         {
@@ -90,8 +90,8 @@ output header {{
       protected:
         /// Constructor
         MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
-                     StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
-                     StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
         {
         }
diff --git a/arch/alpha/isa/pal.isa b/arch/alpha/isa/pal.isa
index b68a7c19f..49e5bff12 100644
--- a/arch/alpha/isa/pal.isa
+++ b/arch/alpha/isa/pal.isa
@@ -149,8 +149,8 @@ output header {{
 
         /// Constructor
         HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
-                    StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
-                    StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
+                    StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+                    StaticInstPtr _memAccPtr = nullStaticInstPtr);
 
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -162,8 +162,8 @@ output decoder {{
     inline
     HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
                              OpClass __opClass,
-                             StaticInstPtr<AlphaISA> _eaCompPtr,
-                             StaticInstPtr<AlphaISA> _memAccPtr)
+                             StaticInstPtr _eaCompPtr,
+                             StaticInstPtr _memAccPtr)
         : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
         disp(HW_LDST_DISP)
     {
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index a6e34acbb..2da37b2e0 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -44,17 +44,16 @@ class Checkpoint;
 
 #define TARGET_ALPHA
 
-template <class ISA> class StaticInst;
-template <class ISA> class StaticInstPtr;
+class StaticInst;
+class StaticInstPtr;
 
 namespace EV5 {
 int DTB_ASN_ASN(uint64_t reg);
 int ITB_ASN_ASN(uint64_t reg);
 }
 
-class AlphaISA
+namespace AlphaISA
 {
-  public:
 
     typedef uint32_t MachInst;
     typedef uint64_t Addr;
@@ -133,10 +132,10 @@ class AlphaISA
         Addr		lock_addr;	// lock address for LL/SC
     } MiscRegFile;
 
-static const Addr PageShift = 13;
-static const Addr PageBytes = ULL(1) << PageShift;
-static const Addr PageMask = ~(PageBytes - 1);
-static const Addr PageOffset = PageBytes - 1;
+extern const Addr PageShift;
+extern const Addr PageBytes;
+extern const Addr PageMask;
+extern const Addr PageOffset;
 
 #if FULL_SYSTEM
 
@@ -184,10 +183,10 @@ static const Addr PageOffset = PageBytes - 1;
         void unserialize(Checkpoint *cp, const std::string &section);
     };
 
-    static StaticInstPtr<AlphaISA> decodeInst(MachInst);
+    StaticInstPtr decodeInst(MachInst);
 
     // return a no-op instruction... used for instruction fetch faults
-    static const MachInst NoopMachInst;
+    extern const MachInst NoopMachInst;
 
     enum annotes {
         ANNOTE_NONE = 0,
@@ -242,10 +241,10 @@ static const Addr PageOffset = PageBytes - 1;
 
     // Machine operations
 
-    static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
+    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
                                int regnum);
 
-    static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
+    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
                                   int regnum);
 
 #if 0
@@ -263,41 +262,41 @@ static const Addr PageOffset = PageBytes - 1;
      * @param xc The execution context.
      */
     template <class XC>
-    static void zeroRegisters(XC *xc);
+    void zeroRegisters(XC *xc);
+
+
+//typedef AlphaISA TheISA;
+
+//typedef TheISA::MachInst MachInst;
+//typedef TheISA::Addr Addr;
+//typedef TheISA::RegIndex RegIndex;
+//typedef TheISA::IntReg IntReg;
+//typedef TheISA::IntRegFile IntRegFile;
+//typedef TheISA::FloatReg FloatReg;
+//typedef TheISA::FloatRegFile FloatRegFile;
+//typedef TheISA::MiscReg MiscReg;
+//typedef TheISA::MiscRegFile MiscRegFile;
+//typedef TheISA::AnyReg AnyReg;
+//typedef TheISA::RegFile RegFile;
+
+//const int NumIntRegs   = TheISA::NumIntRegs;
+//const int NumFloatRegs = TheISA::NumFloatRegs;
+//const int NumMiscRegs  = TheISA::NumMiscRegs;
+//const int TotalNumRegs = TheISA::TotalNumRegs;
+//const int VMPageSize   = TheISA::VMPageSize;
+//const int LogVMPageSize   = TheISA::LogVMPageSize;
+//const int ZeroReg = TheISA::ZeroReg;
+//const int StackPointerReg = TheISA::StackPointerReg;
+//const int GlobalPointerReg = TheISA::GlobalPointerReg;
+//const int ReturnAddressReg = TheISA::ReturnAddressReg;
+//const int ReturnValueReg = TheISA::ReturnValueReg;
+//const int ArgumentReg0 = TheISA::ArgumentReg0;
+//const int ArgumentReg1 = TheISA::ArgumentReg1;
+//const int ArgumentReg2 = TheISA::ArgumentReg2;
+//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const Addr MaxAddr = (Addr)-1;
 };
 
-
-typedef AlphaISA TheISA;
-
-typedef TheISA::MachInst MachInst;
-typedef TheISA::Addr Addr;
-typedef TheISA::RegIndex RegIndex;
-typedef TheISA::IntReg IntReg;
-typedef TheISA::IntRegFile IntRegFile;
-typedef TheISA::FloatReg FloatReg;
-typedef TheISA::FloatRegFile FloatRegFile;
-typedef TheISA::MiscReg MiscReg;
-typedef TheISA::MiscRegFile MiscRegFile;
-typedef TheISA::AnyReg AnyReg;
-typedef TheISA::RegFile RegFile;
-
-const int NumIntRegs   = TheISA::NumIntRegs;
-const int NumFloatRegs = TheISA::NumFloatRegs;
-const int NumMiscRegs  = TheISA::NumMiscRegs;
-const int TotalNumRegs = TheISA::TotalNumRegs;
-const int VMPageSize   = TheISA::VMPageSize;
-const int LogVMPageSize   = TheISA::LogVMPageSize;
-const int ZeroReg = TheISA::ZeroReg;
-const int StackPointerReg = TheISA::StackPointerReg;
-const int GlobalPointerReg = TheISA::GlobalPointerReg;
-const int ReturnAddressReg = TheISA::ReturnAddressReg;
-const int ReturnValueReg = TheISA::ReturnValueReg;
-const int ArgumentReg0 = TheISA::ArgumentReg0;
-const int ArgumentReg1 = TheISA::ArgumentReg1;
-const int ArgumentReg2 = TheISA::ArgumentReg2;
-const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
-const int MaxAddr = (Addr)-1;
-
 #if !FULL_SYSTEM
 class SyscallReturn {
         public:
@@ -336,9 +335,9 @@ class SyscallReturn {
 
 
 #if FULL_SYSTEM
-typedef TheISA::InternalProcReg InternalProcReg;
-const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
-const int NumInterruptLevels = TheISA::NumInterruptLevels;
+//typedef TheISA::InternalProcReg InternalProcReg;
+//const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
+//const int NumInterruptLevels = TheISA::NumInterruptLevels;
 
 #include "arch/alpha/ev5.hh"
 #endif
diff --git a/arch/alpha/stacktrace.cc b/arch/alpha/stacktrace.cc
index 5a8df3d35..30ed07d9d 100644
--- a/arch/alpha/stacktrace.cc
+++ b/arch/alpha/stacktrace.cc
@@ -37,6 +37,7 @@
 #include "cpu/exec_context.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 ProcessInfo::ProcessInfo(ExecContext *_xc)
     : xc(_xc)
@@ -108,7 +109,7 @@ StackTrace::StackTrace()
 {
 }
 
-StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr<TheISA> inst)
+StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst)
     : xc(0), stack(64)
 {
     trace(_xc, inst);
diff --git a/arch/alpha/stacktrace.hh b/arch/alpha/stacktrace.hh
index 244e574b6..211909060 100644
--- a/arch/alpha/stacktrace.hh
+++ b/arch/alpha/stacktrace.hh
@@ -37,6 +37,8 @@ class StackTrace;
 
 class ProcessInfo
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     ExecContext *xc;
 
@@ -56,6 +58,9 @@ class ProcessInfo
 
 class StackTrace
 {
+  protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::MachInst MachInst;
   private:
     ExecContext *xc;
     std::vector<Addr> stack;
@@ -70,7 +75,7 @@ class StackTrace
 
   public:
     StackTrace();
-    StackTrace(ExecContext *xc, StaticInstPtr<TheISA> inst);
+    StackTrace(ExecContext *xc, StaticInstPtr inst);
     ~StackTrace();
 
     void clear()
@@ -80,7 +85,7 @@ class StackTrace
     }
 
     bool valid() const { return xc != NULL; }
-    bool trace(ExecContext *xc, StaticInstPtr<TheISA> inst);
+    bool trace(ExecContext *xc, StaticInstPtr inst);
 
   public:
     const std::vector<Addr> &getstack() const { return stack; }
@@ -102,7 +107,7 @@ class StackTrace
 };
 
 inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr<TheISA> inst)
+StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
 {
     if (!inst->isCall() && !inst->isReturn())
         return false;
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index 27014164c..3ffa4bd14 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -34,6 +34,7 @@
 #include "mem/functional/physical.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 AlphaISA::PageTableEntry
 kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
diff --git a/arch/alpha/vtophys.hh b/arch/alpha/vtophys.hh
index 95430ce77..988f050ba 100644
--- a/arch/alpha/vtophys.hh
+++ b/arch/alpha/vtophys.hh
@@ -35,16 +35,16 @@ class ExecContext;
 class PhysicalMemory;
 
 AlphaISA::PageTableEntry
-kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr);
+kernel_pte_lookup(PhysicalMemory *pmem, AlphaISA::Addr ptbr, AlphaISA::VAddr vaddr);
 
-Addr vtophys(PhysicalMemory *xc, Addr vaddr);
-Addr vtophys(ExecContext *xc, Addr vaddr);
-uint8_t *vtomem(ExecContext *xc, Addr vaddr, size_t len);
-uint8_t *ptomem(ExecContext *xc, Addr paddr, size_t len);
+AlphaISA::Addr vtophys(PhysicalMemory *xc, AlphaISA::Addr vaddr);
+AlphaISA::Addr vtophys(ExecContext *xc, AlphaISA::Addr vaddr);
+uint8_t *vtomem(ExecContext *xc, AlphaISA::Addr vaddr, size_t len);
+uint8_t *ptomem(ExecContext *xc, AlphaISA::Addr paddr, size_t len);
 
-void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
-void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
-void CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
+void CopyOut(ExecContext *xc, void *dst, AlphaISA::Addr src, size_t len);
+void CopyIn(ExecContext *xc, AlphaISA::Addr dst, void *src, size_t len);
+void CopyString(ExecContext *xc, char *dst, AlphaISA::Addr vaddr, size_t maxlen);
 
 #endif // __ARCH_ALPHA_VTOPHYS_H__
 
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 606432e60..864a6a8a7 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -224,7 +224,7 @@ def p_specification(t):
     namespace = isa_name + "Inst"
     # wrap the decode block as a function definition
     t[4].wrap_decode_block('''
-StaticInstPtr<%(isa_name)s>
+StaticInstPtr
 %(isa_name)s::decodeInst(%(isa_name)s::MachInst machInst)
 {
     using namespace %(namespace)s;
@@ -1700,6 +1700,8 @@ namespace %(namespace)s {
 %(namespace_output)s
 
 } // namespace %(namespace)s
+
+%(decode_function)s
 '''
 
 
@@ -1779,13 +1781,15 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
     includes = '#include "base/bitfield.hh" // for bitfield support'
     global_output = global_code.header_output
     namespace_output = namespace_code.header_output
+    decode_function = ''
     update_if_needed(output_dir + '/decoder.hh', file_template % vars())
 
     # generate decoder.cc
     includes = '#include "%s/decoder.hh"' % include_path
     global_output = global_code.decoder_output
     namespace_output = namespace_code.decoder_output
-    namespace_output += namespace_code.decode_block
+    # namespace_output += namespace_code.decode_block
+    decode_function = namespace_code.decode_block
     update_if_needed(output_dir + '/decoder.cc', file_template % vars())
 
     # generate per-cpu exec files
@@ -1794,6 +1798,7 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
         includes += cpu.includes
         global_output = global_code.exec_output[cpu.name]
         namespace_output = namespace_code.exec_output[cpu.name]
+        decode_function = ''
         update_if_needed(output_dir + '/' + cpu.filename,
                           file_template % vars())
 
diff --git a/arch/isa_specific.hh b/arch/isa_specific.hh
new file mode 100644
index 000000000..e11e6c292
--- /dev/null
+++ b/arch/isa_specific.hh
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ISA_SPECIFIC_HH__
+#define __ARCH_ISA_SPECIFIC_HH__
+
+//This file provides a mechanism for other source code to bring in
+//files from the ISA being compiled with
+
+//These are constants so you can selective compile code based on the isa
+//To use them, do something like
+//
+//#if THE_ISA == YOUR_FAVORITE_ISA
+//	conditional_code
+//#endif
+//
+//Note that this is how this file sets up the other isa "hooks"
+
+//These macros have numerical values because otherwise the preprocessor
+//would treat them as 0 in comparisons.
+#define ALPHA_ISA 21064
+#define SPARC_ISA 42
+#define MIPS_ISA 1337
+
+//These tell the preprocessor where to find the files of a particular
+//ISA, and set the "TheISA" macro for use elsewhere.
+#if THE_ISA == ALPHA_ISA
+    #define ISA_PATH arch/alpha/
+    #define TheISA AlphaISA
+#elif THE_ISA == SPARC_ISA
+    #define ISA_PATH arch/sparc/
+    #define TheISA SparcISA
+#elif THE_ISA == MIPS_ISA
+    #define ISA_PATH arch/mips/
+    #define TheISA MipsISA
+#else
+    #error "THE_ISA not set"
+#endif
+//The following is some preprocessor voodoo to allow redirectable includes
+//The end result is the ISA_INCLUDE() macro which is used inside stub
+//include files in arch and which redirect to the isa in use.
+#define STRINGIFY(token) #token
+#define EXPAND(token) token
+#define STICK_TOGETHER(firstpart, secondpart) \
+    EXPAND(firstpart)EXPAND(secondpart)
+#define EXPAND_AND_STRINGIFY(pathAndFile) \
+    STRINGIFY(pathAndFile)
+#define ISA_INCLUDE(filename) \
+    EXPAND_AND_STRINGIFY(STICK_TOGETHER(ISA_PATH, filename))
+
+#endif
diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh
index 3c8659e18..e90f93847 100644
--- a/base/loader/object_file.hh
+++ b/base/loader/object_file.hh
@@ -37,6 +37,7 @@ class SymbolTable;
 class ObjectFile
 {
   public:
+    typedef TheISA::Addr Addr;
 
     enum Arch {
         UnknownArch,
diff --git a/base/loader/symtab.hh b/base/loader/symtab.hh
index ebcda1345..38b4cdee2 100644
--- a/base/loader/symtab.hh
+++ b/base/loader/symtab.hh
@@ -37,8 +37,9 @@
 class Checkpoint;
 class SymbolTable
 {
+    typedef TheISA::Addr Addr;
   public:
-    typedef std::map<Addr, std::string> ATable;
+    typedef std::map<TheISA::Addr, std::string> ATable;
     typedef std::map<std::string, Addr> STable;
 
   private:
diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc
index 67d745d43..17ec21fed 100644
--- a/base/remote_gdb.cc
+++ b/base/remote_gdb.cc
@@ -132,6 +132,7 @@
 #include "targetarch/vtophys.hh"
 
 using namespace std;
+using namespace TheISA;
 
 #ifndef NDEBUG
 vector<RemoteGDB *> debuggers;
@@ -494,7 +495,7 @@ RemoteGDB::setSingleStep()
     // User was stopped at pc, e.g. the instruction at pc was not
     // executed.
     MachInst inst = read<MachInst>(pc);
-    StaticInstPtr<TheISA> si(inst);
+    StaticInstPtr si(inst);
     if (si->hasBranchTarget(pc, context, bpc)) {
         // Don't bother setting a breakpoint on the taken branch if it
         // is the same as the next pc
diff --git a/base/remote_gdb.hh b/base/remote_gdb.hh
index 652a58317..126d5f6f8 100644
--- a/base/remote_gdb.hh
+++ b/base/remote_gdb.hh
@@ -43,6 +43,9 @@ class PhysicalMemory;
 class GDBListener;
 class RemoteGDB
 {
+  protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::MachInst MachInst;
   private:
     friend void debugger();
     friend class GDBListener;
diff --git a/cpu/base.cc b/cpu/base.cc
index 8b94b8533..5a7ecf152 100644
--- a/cpu/base.cc
+++ b/cpu/base.cc
@@ -250,7 +250,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
     }
 
 #if FULL_SYSTEM
-    for (int i = 0; i < NumInterruptLevels; ++i)
+    for (int i = 0; i < TheISA::NumInterruptLevels; ++i)
         interrupts[i] = oldCPU->interrupts[i];
     intstatus = oldCPU->intstatus;
 
@@ -285,7 +285,7 @@ BaseCPU::post_interrupt(int int_num, int index)
 {
     DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
 
-    if (int_num < 0 || int_num >= NumInterruptLevels)
+    if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
         panic("int_num out of bounds\n");
 
     if (index < 0 || index >= sizeof(uint64_t) * 8)
@@ -301,7 +301,7 @@ BaseCPU::clear_interrupt(int int_num, int index)
 {
     DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
 
-    if (int_num < 0 || int_num >= NumInterruptLevels)
+    if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
         panic("int_num out of bounds\n");
 
     if (index < 0 || index >= sizeof(uint64_t) * 8)
@@ -325,14 +325,14 @@ BaseCPU::clear_interrupts()
 void
 BaseCPU::serialize(std::ostream &os)
 {
-    SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+    SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
     SERIALIZE_SCALAR(intstatus);
 }
 
 void
 BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
 {
-    UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+    UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
     UNSERIALIZE_SCALAR(intstatus);
 }
 
diff --git a/cpu/base.hh b/cpu/base.hh
index 09a73ab16..82a47bf4c 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -48,6 +48,7 @@ class ExecContext;
 class BaseCPU : public SimObject
 {
   protected:
+    typedef TheISA::Addr Addr;
     // CPU's clock period in terms of the number of ticks of curTime.
     Tick clock;
 
@@ -58,7 +59,7 @@ class BaseCPU : public SimObject
 
 #if FULL_SYSTEM
   protected:
-    uint64_t interrupts[NumInterruptLevels];
+    uint64_t interrupts[TheISA::NumInterruptLevels];
     uint64_t intstatus;
 
   public:
@@ -68,7 +69,7 @@ class BaseCPU : public SimObject
     bool checkInterrupts;
 
     bool check_interrupt(int int_num) const {
-        if (int_num > NumInterruptLevels)
+        if (int_num > TheISA::NumInterruptLevels)
             panic("int_num out of bounds\n");
 
         return interrupts[int_num] != 0;
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 59a12f2d0..9901c90af 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -79,7 +79,7 @@ BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
 }
 
 template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
     : staticInst(_staticInst), traceData(NULL)
 {
     initVars();
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index 2c91db99c..dd429fc91 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -51,7 +51,6 @@
  */
 
 // Forward declaration.
-template <class ISA>
 class StaticInstPtr;
 
 template <class Impl>
@@ -61,25 +60,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
     // Typedef for the CPU.
     typedef typename Impl::FullCPU FullCPU;
 
-    //Typedef to get the ISA.
-    typedef typename Impl::ISA ISA;
-
     /// Binary machine instruction type.
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
     /// Memory address type.
-    typedef typename ISA::Addr	   Addr;
+    typedef TheISA::Addr Addr;
     /// Logical register index type.
-    typedef typename ISA::RegIndex RegIndex;
+    typedef TheISA::RegIndex RegIndex;
     /// Integer register index type.
-    typedef typename ISA::IntReg   IntReg;
+    typedef TheISA::IntReg IntReg;
 
     enum {
-        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
-        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
+        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
     };
 
     /** The static inst used by this dyn inst. */
-    StaticInstPtr<ISA> staticInst;
+    StaticInstPtr staticInst;
 
     ////////////////////////////////////////////
     //
@@ -214,7 +210,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
                 FullCPU *cpu);
 
     /** BaseDynInst constructor given a static inst pointer. */
-    BaseDynInst(StaticInstPtr<ISA> &_staticInst);
+    BaseDynInst(StaticInstPtr &_staticInst);
 
     /** BaseDynInst destructor. */
     ~BaseDynInst();
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 845f9264b..f11d69273 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -35,6 +35,7 @@
 #include "sim/host.hh"
 #include "sim/serialize.hh"
 #include "arch/isa_traits.hh"
+//#include "arch/isa_registers.hh"
 #include "sim/byteswap.hh"
 
 // forward declaration: see functional_memory.hh
@@ -66,6 +67,11 @@ namespace Kernel { class Binning; class Statistics; }
 
 class ExecContext
 {
+  protected:
+    typedef TheISA::RegFile RegFile;
+    typedef TheISA::Addr Addr;
+    typedef TheISA::MachInst MachInst;
+    typedef TheISA::MiscRegFile MiscRegFile;
   public:
     enum Status
     {
@@ -433,15 +439,15 @@ class ExecContext
     void trap(Fault fault);
 
 #if !FULL_SYSTEM
-    IntReg getSyscallArg(int i)
+    TheISA::IntReg getSyscallArg(int i)
     {
-        return regs.intRegFile[ArgumentReg0 + i];
+        return regs.intRegFile[TheISA::ArgumentReg0 + i];
     }
 
     // used to shift args for indirect syscall
-    void setSyscallArg(int i, IntReg val)
+    void setSyscallArg(int i, TheISA::IntReg val)
     {
-        regs.intRegFile[ArgumentReg0 + i] = val;
+        regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
     }
 
     void setSyscallReturn(SyscallReturn return_value)
@@ -453,11 +459,11 @@ class ExecContext
         if (return_value.successful()) {
             // no error
             regs.intRegFile[RegA3] = 0;
-            regs.intRegFile[ReturnValueReg] = return_value.value();
+            regs.intRegFile[TheISA::ReturnValueReg] = return_value.value();
         } else {
             // got an error, return details
-            regs.intRegFile[RegA3] = (IntReg) -1;
-            regs.intRegFile[ReturnValueReg] = -return_value.value();
+            regs.intRegFile[RegA3] = (TheISA::IntReg) -1;
+            regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value();
         }
     }
 
diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh
index 48d8966d8..d37c48ddd 100644
--- a/cpu/exetrace.hh
+++ b/cpu/exetrace.hh
@@ -46,13 +46,15 @@ namespace Trace {
 class InstRecord : public Record
 {
   protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::IntRegFile IntRegFile;
 
     // The following fields are initialized by the constructor and
     // thus guaranteed to be valid.
     BaseCPU *cpu;
     // need to make this ref-counted so it doesn't go away before we
     // dump the record
-    StaticInstPtr<TheISA> staticInst;
+    StaticInstPtr staticInst;
     Addr PC;
     bool misspeculating;
     unsigned thread;
@@ -92,7 +94,7 @@ class InstRecord : public Record
 
   public:
     InstRecord(Tick _cycle, BaseCPU *_cpu,
-               const StaticInstPtr<TheISA> &_staticInst,
+               const StaticInstPtr &_staticInst,
                Addr _pc, bool spec, int _thread)
         : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
           misspeculating(spec), thread(_thread)
@@ -169,8 +171,8 @@ InstRecord::setRegs(const IntRegFile &regs)
 inline
 InstRecord *
 getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
-              const StaticInstPtr<TheISA> staticInst,
-              Addr pc, int thread = 0)
+              const StaticInstPtr staticInst,
+              TheISA::Addr pc, int thread = 0)
 {
     if (DTRACE(InstExec) &&
         (InstRecord::traceMisspec() || !xc->misspeculating())) {
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 27f790fac..5a4024587 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -44,6 +44,7 @@
 #include "sim/stats.hh"
 
 using namespace std;
+using namespace TheISA;
 
 int TESTER_ALLOCATOR=0;
 
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 7abcf017a..76a89ff2c 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -42,6 +42,8 @@
 class ExecContext;
 class MemTest : public SimObject
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
 
     MemTest(const std::string &name,
diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh
index a97ce455c..78efe1e43 100644
--- a/cpu/o3/2bit_local_pred.hh
+++ b/cpu/o3/2bit_local_pred.hh
@@ -30,11 +30,13 @@
 #define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/o3/sat_counter.hh"
 
 class DefaultBP
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     /**
      * Default branch predictor constructor.
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 606f9fa0a..bf3556b8e 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -39,8 +39,10 @@
 template <class Impl>
 class AlphaFullCPU : public FullO3CPU<Impl>
 {
+  protected:
+    typedef AlphaISA::Addr Addr;
+    typedef TheISA::IntReg IntReg;
   public:
-    typedef typename Impl::ISA AlphaISA;
     typedef typename Impl::Params Params;
 
   public:
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 408676331..6736cf9bc 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -282,7 +282,7 @@ AlphaFullCPU<Impl>::hwrei()
     if (!inPalMode())
         return UnimplementedOpcodeFault;
 
-    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+    this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
 //    kernelStats.hwrei();
 
@@ -337,7 +337,7 @@ AlphaFullCPU<Impl>::trap(Fault * fault)
     if (fault == ArithmeticFault)
         panic("Arithmetic traps are unimplemented!");
 
-    typename AlphaISA::InternalProcReg *ipr = getIpr();
+    AlphaISA::InternalProcReg *ipr = getIpr();
 
     // exception restart address - Get the commit PC
     if (fault != InterruptFault || !inPalMode(PC))
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index 77dcbaf74..22be2aae5 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -48,21 +48,18 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** Typedef for the CPU. */
     typedef typename Impl::FullCPU FullCPU;
 
-    /** Typedef to get the ISA. */
-    typedef typename Impl::ISA ISA;
-
     /** Binary machine instruction type. */
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
     /** Memory address type. */
-    typedef typename ISA::Addr	   Addr;
+    typedef TheISA::Addr	   Addr;
     /** Logical register index type. */
-    typedef typename ISA::RegIndex RegIndex;
+    typedef TheISA::RegIndex RegIndex;
     /** Integer register index type. */
-    typedef typename ISA::IntReg   IntReg;
+    typedef TheISA::IntReg   IntReg;
 
     enum {
-        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
-        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
+        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
     };
 
   public:
@@ -71,7 +68,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
                  FullCPU *cpu);
 
     /** BaseDynInst constructor given a static inst pointer. */
-    AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
+    AlphaDynInst(StaticInstPtr &_staticInst);
 
     /** Executes the instruction.*/
     Fault * execute()
@@ -130,22 +127,22 @@ class AlphaDynInst : public BaseDynInst<Impl>
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst<ISA> *si, int idx)
+    uint64_t readIntReg(const StaticInst *si, int idx)
     {
         return this->cpu->readIntReg(_srcRegIdx[idx]);
     }
 
-    float readFloatRegSingle(const StaticInst<ISA> *si, int idx)
+    float readFloatRegSingle(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
     }
 
-    double readFloatRegDouble(const StaticInst<ISA> *si, int idx)
+    double readFloatRegDouble(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
     }
 
-    uint64_t readFloatRegInt(const StaticInst<ISA> *si, int idx)
+    uint64_t readFloatRegInt(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
     }
@@ -153,25 +150,25 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
-    void setIntReg(const StaticInst<ISA> *si, int idx, uint64_t val)
+    void setIntReg(const StaticInst *si, int idx, uint64_t val)
     {
         this->cpu->setIntReg(_destRegIdx[idx], val);
         this->instResult.integer = val;
     }
 
-    void setFloatRegSingle(const StaticInst<ISA> *si, int idx, float val)
+    void setFloatRegSingle(const StaticInst *si, int idx, float val)
     {
         this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
         this->instResult.fp = val;
     }
 
-    void setFloatRegDouble(const StaticInst<ISA> *si, int idx, double val)
+    void setFloatRegDouble(const StaticInst *si, int idx, double val)
     {
         this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
         this->instResult.dbl = val;
     }
 
-    void setFloatRegInt(const StaticInst<ISA> *si, int idx, uint64_t val)
+    void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
     {
         this->cpu->setFloatRegInt(_destRegIdx[idx], val);
         this->instResult.integer = val;
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index b20af48cd..9f9df3da1 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -50,7 +50,7 @@ AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
 }
 
 template <class Impl>
-AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
+AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
     : BaseDynInst<Impl>(_staticInst)
 {
     // Make sure to have the renamed register entries set to the same
diff --git a/cpu/o3/alpha_impl.hh b/cpu/o3/alpha_impl.hh
index 6c1156041..5e39fcb37 100644
--- a/cpu/o3/alpha_impl.hh
+++ b/cpu/o3/alpha_impl.hh
@@ -51,11 +51,8 @@ class AlphaFullCPU;
  */
 struct AlphaSimpleImpl
 {
-    /** The ISA to be used. */
-    typedef AlphaISA ISA;
-
     /** The type of MachInst. */
-    typedef ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
 
     /** The CPU policy to be used (ie fetch, decode, etc.). */
     typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 0a77b83dc..c874f9e04 100644
--- a/cpu/o3/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -53,6 +53,8 @@
 template<class Impl>
 class TwobitBPredUnit
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
diff --git a/cpu/o3/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh
index 9cb2e0490..8d16a0cdf 100644
--- a/cpu/o3/bpred_unit_impl.hh
+++ b/cpu/o3/bpred_unit_impl.hh
@@ -98,6 +98,8 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
     // Save off record of branch stuff so the RAS can be fixed
     // up once it's done.
 
+    using TheISA::MachInst;
+
     bool pred_taken = false;
     Addr target;
 
diff --git a/cpu/o3/btb.cc b/cpu/o3/btb.cc
index 7671e61e2..2d39c3856 100644
--- a/cpu/o3/btb.cc
+++ b/cpu/o3/btb.cc
@@ -30,6 +30,8 @@
 #include "base/trace.hh"
 #include "cpu/o3/btb.hh"
 
+using namespace TheISA;
+
 DefaultBTB::DefaultBTB(unsigned _numEntries,
                        unsigned _tagBits,
                        unsigned _instShiftAmt)
diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh
index a4ddfecb4..f443ddbaf 100644
--- a/cpu/o3/btb.hh
+++ b/cpu/o3/btb.hh
@@ -30,10 +30,12 @@
 #define __CPU_O3_CPU_BTB_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 
 class DefaultBTB
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     struct BTBEntry
     {
diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh
index 6ddc8d6b9..580c1a316 100644
--- a/cpu/o3/commit.hh
+++ b/cpu/o3/commit.hh
@@ -52,7 +52,6 @@ class SimpleCommit
 {
   public:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::Params Params;
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index adc7b6bbc..ffa157fbb 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -84,14 +84,14 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
       regFile(params.numPhysIntRegs, params.numPhysFloatRegs),
 
-      freeList(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
-               Impl::ISA::NumFloatRegs, params.numPhysFloatRegs),
+      freeList(TheISA::NumIntRegs, params.numPhysIntRegs,
+               TheISA::NumFloatRegs, params.numPhysFloatRegs),
 
-      renameMap(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
-                Impl::ISA::NumFloatRegs, params.numPhysFloatRegs,
-                Impl::ISA::NumMiscRegs,
-                Impl::ISA::ZeroReg,
-                Impl::ISA::ZeroReg + Impl::ISA::NumIntRegs),
+      renameMap(TheISA::NumIntRegs, params.numPhysIntRegs,
+                TheISA::NumFloatRegs, params.numPhysFloatRegs,
+                TheISA::NumMiscRegs,
+                TheISA::ZeroReg,
+                TheISA::ZeroReg + TheISA::NumIntRegs),
 
       rob(params.numROBEntries, params.squashWidth),
 
@@ -254,13 +254,13 @@ FullO3CPU<Impl>::init()
         ExecContext *src_xc = thread[0];
 #endif
         // First loop through the integer registers.
-        for (int i = 0; i < Impl::ISA::NumIntRegs; ++i)
+        for (int i = 0; i < TheISA::NumIntRegs; ++i)
         {
             regFile.intRegFile[i] = src_xc->regs.intRegFile[i];
         }
 
         // Then loop through the floating point registers.
-        for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i)
+        for (int i = 0; i < TheISA::NumFloatRegs; ++i)
         {
             regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
             regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 75dca5056..321d61dce 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -78,7 +78,6 @@ class FullO3CPU : public BaseFullCPU
 {
   public:
     //Put typedefs from the Impl here.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPolicy;
     typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -153,11 +152,11 @@ class FullO3CPU : public BaseFullCPU
 
     /** Get instruction asid. */
     int getInstAsid()
-    { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); }
+    { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); }
 
     /** Get data asid. */
     int getDataAsid()
-    { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); }
+    { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); }
 #else
     bool validInstAddr(Addr addr)
     { return thread[0]->validInstAddr(addr); }
diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh
index 42313d83a..bae9a7015 100644
--- a/cpu/o3/decode.hh
+++ b/cpu/o3/decode.hh
@@ -39,7 +39,6 @@ class SimpleDecode
 {
   private:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::Params Params;
@@ -51,7 +50,7 @@ class SimpleDecode
     typedef typename CPUPol::TimeStruct TimeStruct;
 
     // Typedefs from the ISA.
-    typedef typename ISA::Addr Addr;
+    typedef TheISA::Addr Addr;
 
   public:
     // The only time decode will become blocked is if dispatch becomes
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 5443d274e..e4d374c1d 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -49,7 +49,6 @@ class SimpleFetch
 {
   public:
     /** Typedefs from Impl. */
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInst DynInst;
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -61,7 +60,8 @@ class SimpleFetch
     typedef typename CPUPol::TimeStruct TimeStruct;
 
     /** Typedefs from ISA. */
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
+    typedef TheISA::Addr Addr;
 
   public:
     enum Status {
@@ -141,7 +141,7 @@ class SimpleFetch
     // We fold in the PISA 64- to 32-bit conversion here as well.
     Addr icacheBlockAlignPC(Addr addr)
     {
-        addr = ISA::realPCToFetchPC(addr);
+        addr = TheISA::realPCToFetchPC(addr);
         return (addr & ~(cacheBlkMask));
     }
 
diff --git a/cpu/o3/free_list.hh b/cpu/o3/free_list.hh
index 733d142fc..0b85dba1e 100644
--- a/cpu/o3/free_list.hh
+++ b/cpu/o3/free_list.hh
@@ -32,7 +32,7 @@
 #include <iostream>
 #include <queue>
 
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
 #include "cpu/o3/comm.hh"
diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index af23c6f45..1e370d4e6 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -45,7 +45,6 @@ class SimpleIEW
 {
   private:
     //Typedefs from Impl
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index b8a2b4dc9..85217dd10 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -256,7 +256,7 @@ SimpleIEW<Impl>::squashDueToBranch(DynInstPtr &inst)
     toCommit->branchMispredict = true;
     // Prediction was incorrect, so send back inverse.
     toCommit->branchTaken = inst->readNextPC() !=
-        (inst->readPC() + sizeof(MachInst));
+        (inst->readPC() + sizeof(TheISA::MachInst));
 }
 
 template<class Impl>
diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh
index bbc4162a6..fd7f5fe1c 100644
--- a/cpu/o3/ras.hh
+++ b/cpu/o3/ras.hh
@@ -30,10 +30,12 @@
 #define __CPU_O3_CPU_RAS_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 
 class ReturnAddrStack
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     ReturnAddrStack(unsigned numEntries);
 
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 5aafd5495..655a3cad9 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -52,6 +52,11 @@ using namespace EV5;
 template <class Impl>
 class PhysRegFile
 {
+  protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::IntReg IntReg;
+    typedef TheISA::FloatReg FloatReg;
+    typedef TheISA::MiscRegFile MiscRegFile;
     //Note that most of the definitions of the IntReg, FloatReg, etc. exist
     //within the Impl/ISA class and not within this PhysRegFile class.
 
@@ -62,7 +67,6 @@ class PhysRegFile
     //Will make these registers public for now, but they probably should
     //be private eventually with some accessor functions.
   public:
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
 
     PhysRegFile(unsigned _numPhysicalIntRegs,
@@ -281,73 +285,73 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
     uint64_t retval = 0;    // return value, default 0
 
     switch (idx) {
-      case ISA::IPR_PALtemp0:
-      case ISA::IPR_PALtemp1:
-      case ISA::IPR_PALtemp2:
-      case ISA::IPR_PALtemp3:
-      case ISA::IPR_PALtemp4:
-      case ISA::IPR_PALtemp5:
-      case ISA::IPR_PALtemp6:
-      case ISA::IPR_PALtemp7:
-      case ISA::IPR_PALtemp8:
-      case ISA::IPR_PALtemp9:
-      case ISA::IPR_PALtemp10:
-      case ISA::IPR_PALtemp11:
-      case ISA::IPR_PALtemp12:
-      case ISA::IPR_PALtemp13:
-      case ISA::IPR_PALtemp14:
-      case ISA::IPR_PALtemp15:
-      case ISA::IPR_PALtemp16:
-      case ISA::IPR_PALtemp17:
-      case ISA::IPR_PALtemp18:
-      case ISA::IPR_PALtemp19:
-      case ISA::IPR_PALtemp20:
-      case ISA::IPR_PALtemp21:
-      case ISA::IPR_PALtemp22:
-      case ISA::IPR_PALtemp23:
-      case ISA::IPR_PAL_BASE:
-
-      case ISA::IPR_IVPTBR:
-      case ISA::IPR_DC_MODE:
-      case ISA::IPR_MAF_MODE:
-      case ISA::IPR_ISR:
-      case ISA::IPR_EXC_ADDR:
-      case ISA::IPR_IC_PERR_STAT:
-      case ISA::IPR_DC_PERR_STAT:
-      case ISA::IPR_MCSR:
-      case ISA::IPR_ASTRR:
-      case ISA::IPR_ASTER:
-      case ISA::IPR_SIRR:
-      case ISA::IPR_ICSR:
-      case ISA::IPR_ICM:
-      case ISA::IPR_DTB_CM:
-      case ISA::IPR_IPLR:
-      case ISA::IPR_INTID:
-      case ISA::IPR_PMCTR:
+      case TheISA::IPR_PALtemp0:
+      case TheISA::IPR_PALtemp1:
+      case TheISA::IPR_PALtemp2:
+      case TheISA::IPR_PALtemp3:
+      case TheISA::IPR_PALtemp4:
+      case TheISA::IPR_PALtemp5:
+      case TheISA::IPR_PALtemp6:
+      case TheISA::IPR_PALtemp7:
+      case TheISA::IPR_PALtemp8:
+      case TheISA::IPR_PALtemp9:
+      case TheISA::IPR_PALtemp10:
+      case TheISA::IPR_PALtemp11:
+      case TheISA::IPR_PALtemp12:
+      case TheISA::IPR_PALtemp13:
+      case TheISA::IPR_PALtemp14:
+      case TheISA::IPR_PALtemp15:
+      case TheISA::IPR_PALtemp16:
+      case TheISA::IPR_PALtemp17:
+      case TheISA::IPR_PALtemp18:
+      case TheISA::IPR_PALtemp19:
+      case TheISA::IPR_PALtemp20:
+      case TheISA::IPR_PALtemp21:
+      case TheISA::IPR_PALtemp22:
+      case TheISA::IPR_PALtemp23:
+      case TheISA::IPR_PAL_BASE:
+
+      case TheISA::IPR_IVPTBR:
+      case TheISA::IPR_DC_MODE:
+      case TheISA::IPR_MAF_MODE:
+      case TheISA::IPR_ISR:
+      case TheISA::IPR_EXC_ADDR:
+      case TheISA::IPR_IC_PERR_STAT:
+      case TheISA::IPR_DC_PERR_STAT:
+      case TheISA::IPR_MCSR:
+      case TheISA::IPR_ASTRR:
+      case TheISA::IPR_ASTER:
+      case TheISA::IPR_SIRR:
+      case TheISA::IPR_ICSR:
+      case TheISA::IPR_ICM:
+      case TheISA::IPR_DTB_CM:
+      case TheISA::IPR_IPLR:
+      case TheISA::IPR_INTID:
+      case TheISA::IPR_PMCTR:
         // no side-effect
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_CC:
+      case TheISA::IPR_CC:
         retval |= ipr[idx] & ULL(0xffffffff00000000);
         retval |= curTick  & ULL(0x00000000ffffffff);
         break;
 
-      case ISA::IPR_VA:
+      case TheISA::IPR_VA:
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_VA_FORM:
-      case ISA::IPR_MM_STAT:
-      case ISA::IPR_IFAULT_VA_FORM:
-      case ISA::IPR_EXC_MASK:
-      case ISA::IPR_EXC_SUM:
+      case TheISA::IPR_VA_FORM:
+      case TheISA::IPR_MM_STAT:
+      case TheISA::IPR_IFAULT_VA_FORM:
+      case TheISA::IPR_EXC_MASK:
+      case TheISA::IPR_EXC_SUM:
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_DTB_PTE:
+      case TheISA::IPR_DTB_PTE:
         {
-            typename ISA::PTE &pte = cpu->dtb->index(1);
+            TheISA::PTE &pte = cpu->dtb->index(1);
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -360,15 +364,15 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
         break;
 
         // write only registers
-      case ISA::IPR_HWINT_CLR:
-      case ISA::IPR_SL_XMIT:
-      case ISA::IPR_DC_FLUSH:
-      case ISA::IPR_IC_FLUSH:
-      case ISA::IPR_ALT_MODE:
-      case ISA::IPR_DTB_IA:
-      case ISA::IPR_DTB_IAP:
-      case ISA::IPR_ITB_IA:
-      case ISA::IPR_ITB_IAP:
+      case TheISA::IPR_HWINT_CLR:
+      case TheISA::IPR_SL_XMIT:
+      case TheISA::IPR_DC_FLUSH:
+      case TheISA::IPR_IC_FLUSH:
+      case TheISA::IPR_ALT_MODE:
+      case TheISA::IPR_DTB_IA:
+      case TheISA::IPR_DTB_IAP:
+      case TheISA::IPR_ITB_IA:
+      case TheISA::IPR_ITB_IAP:
         fault = UnimplementedOpcodeFault;
         break;
 
@@ -390,195 +394,195 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
     uint64_t old;
 
     switch (idx) {
-      case ISA::IPR_PALtemp0:
-      case ISA::IPR_PALtemp1:
-      case ISA::IPR_PALtemp2:
-      case ISA::IPR_PALtemp3:
-      case ISA::IPR_PALtemp4:
-      case ISA::IPR_PALtemp5:
-      case ISA::IPR_PALtemp6:
-      case ISA::IPR_PALtemp7:
-      case ISA::IPR_PALtemp8:
-      case ISA::IPR_PALtemp9:
-      case ISA::IPR_PALtemp10:
-      case ISA::IPR_PALtemp11:
-      case ISA::IPR_PALtemp12:
-      case ISA::IPR_PALtemp13:
-      case ISA::IPR_PALtemp14:
-      case ISA::IPR_PALtemp15:
-      case ISA::IPR_PALtemp16:
-      case ISA::IPR_PALtemp17:
-      case ISA::IPR_PALtemp18:
-      case ISA::IPR_PALtemp19:
-      case ISA::IPR_PALtemp20:
-      case ISA::IPR_PALtemp21:
-      case ISA::IPR_PALtemp22:
-      case ISA::IPR_PAL_BASE:
-      case ISA::IPR_IC_PERR_STAT:
-      case ISA::IPR_DC_PERR_STAT:
-      case ISA::IPR_PMCTR:
+      case TheISA::IPR_PALtemp0:
+      case TheISA::IPR_PALtemp1:
+      case TheISA::IPR_PALtemp2:
+      case TheISA::IPR_PALtemp3:
+      case TheISA::IPR_PALtemp4:
+      case TheISA::IPR_PALtemp5:
+      case TheISA::IPR_PALtemp6:
+      case TheISA::IPR_PALtemp7:
+      case TheISA::IPR_PALtemp8:
+      case TheISA::IPR_PALtemp9:
+      case TheISA::IPR_PALtemp10:
+      case TheISA::IPR_PALtemp11:
+      case TheISA::IPR_PALtemp12:
+      case TheISA::IPR_PALtemp13:
+      case TheISA::IPR_PALtemp14:
+      case TheISA::IPR_PALtemp15:
+      case TheISA::IPR_PALtemp16:
+      case TheISA::IPR_PALtemp17:
+      case TheISA::IPR_PALtemp18:
+      case TheISA::IPR_PALtemp19:
+      case TheISA::IPR_PALtemp20:
+      case TheISA::IPR_PALtemp21:
+      case TheISA::IPR_PALtemp22:
+      case TheISA::IPR_PAL_BASE:
+      case TheISA::IPR_IC_PERR_STAT:
+      case TheISA::IPR_DC_PERR_STAT:
+      case TheISA::IPR_PMCTR:
         // write entire quad w/ no side-effect
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_CC_CTL:
+      case TheISA::IPR_CC_CTL:
         // This IPR resets the cycle counter.  We assume this only
         // happens once... let's verify that.
         assert(ipr[idx] == 0);
         ipr[idx] = 1;
         break;
 
-      case ISA::IPR_CC:
+      case TheISA::IPR_CC:
         // This IPR only writes the upper 64 bits.  It's ok to write
         // all 64 here since we mask out the lower 32 in rpcc (see
         // isa_desc).
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_PALtemp23:
+      case TheISA::IPR_PALtemp23:
         // write entire quad w/ no side-effect
         old = ipr[idx];
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_DTB_PTE:
+      case TheISA::IPR_DTB_PTE:
         // write entire quad w/ no side-effect, tag is forthcoming
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_EXC_ADDR:
+      case TheISA::IPR_EXC_ADDR:
         // second least significant bit in PC is always zero
         ipr[idx] = val & ~2;
         break;
 
-      case ISA::IPR_ASTRR:
-      case ISA::IPR_ASTER:
+      case TheISA::IPR_ASTRR:
+      case TheISA::IPR_ASTER:
         // only write least significant four bits - privilege mask
         ipr[idx] = val & 0xf;
         break;
 
-      case ISA::IPR_IPLR:
+      case TheISA::IPR_IPLR:
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
         break;
 
-      case ISA::IPR_DTB_CM:
+      case TheISA::IPR_DTB_CM:
 
-      case ISA::IPR_ICM:
+      case TheISA::IPR_ICM:
         // only write two mode bits - processor mode
         ipr[idx] = val & 0x18;
         break;
 
-      case ISA::IPR_ALT_MODE:
+      case TheISA::IPR_ALT_MODE:
         // only write two mode bits - processor mode
         ipr[idx] = val & 0x18;
         break;
 
-      case ISA::IPR_MCSR:
+      case TheISA::IPR_MCSR:
         // more here after optimization...
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_SIRR:
+      case TheISA::IPR_SIRR:
         // only write software interrupt mask
         ipr[idx] = val & 0x7fff0;
         break;
 
-      case ISA::IPR_ICSR:
+      case TheISA::IPR_ICSR:
         ipr[idx] = val & ULL(0xffffff0300);
         break;
 
-      case ISA::IPR_IVPTBR:
-      case ISA::IPR_MVPTBR:
+      case TheISA::IPR_IVPTBR:
+      case TheISA::IPR_MVPTBR:
         ipr[idx] = val & ULL(0xffffffffc0000000);
         break;
 
-      case ISA::IPR_DC_TEST_CTL:
+      case TheISA::IPR_DC_TEST_CTL:
         ipr[idx] = val & 0x1ffb;
         break;
 
-      case ISA::IPR_DC_MODE:
-      case ISA::IPR_MAF_MODE:
+      case TheISA::IPR_DC_MODE:
+      case TheISA::IPR_MAF_MODE:
         ipr[idx] = val & 0x3f;
         break;
 
-      case ISA::IPR_ITB_ASN:
+      case TheISA::IPR_ITB_ASN:
         ipr[idx] = val & 0x7f0;
         break;
 
-      case ISA::IPR_DTB_ASN:
+      case TheISA::IPR_DTB_ASN:
         ipr[idx] = val & ULL(0xfe00000000000000);
         break;
 
-      case ISA::IPR_EXC_SUM:
-      case ISA::IPR_EXC_MASK:
+      case TheISA::IPR_EXC_SUM:
+      case TheISA::IPR_EXC_MASK:
         // any write to this register clears it
         ipr[idx] = 0;
         break;
 
-      case ISA::IPR_INTID:
-      case ISA::IPR_SL_RCV:
-      case ISA::IPR_MM_STAT:
-      case ISA::IPR_ITB_PTE_TEMP:
-      case ISA::IPR_DTB_PTE_TEMP:
+      case TheISA::IPR_INTID:
+      case TheISA::IPR_SL_RCV:
+      case TheISA::IPR_MM_STAT:
+      case TheISA::IPR_ITB_PTE_TEMP:
+      case TheISA::IPR_DTB_PTE_TEMP:
         // read-only registers
         return UnimplementedOpcodeFault;
 
-      case ISA::IPR_HWINT_CLR:
-      case ISA::IPR_SL_XMIT:
-      case ISA::IPR_DC_FLUSH:
-      case ISA::IPR_IC_FLUSH:
+      case TheISA::IPR_HWINT_CLR:
+      case TheISA::IPR_SL_XMIT:
+      case TheISA::IPR_DC_FLUSH:
+      case TheISA::IPR_IC_FLUSH:
         // the following are write only
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_DTB_IA:
+      case TheISA::IPR_DTB_IA:
         // really a control write
         ipr[idx] = 0;
 
         cpu->dtb->flushAll();
         break;
 
-      case ISA::IPR_DTB_IAP:
+      case TheISA::IPR_DTB_IAP:
         // really a control write
         ipr[idx] = 0;
 
         cpu->dtb->flushProcesses();
         break;
 
-      case ISA::IPR_DTB_IS:
+      case TheISA::IPR_DTB_IS:
         // really a control write
         ipr[idx] = val;
 
-        cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
+        cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
         break;
 
-      case ISA::IPR_DTB_TAG: {
-          struct ISA::PTE pte;
+      case TheISA::IPR_DTB_TAG: {
+          struct TheISA::PTE pte;
 
           // FIXME: granularity hints NYI...
-          if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
+          if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
               panic("PTE GH field != 0");
 
           // write entire quad
           ipr[idx] = val;
 
           // construct PTE for new entry
-          pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
-          pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
-          pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
-          pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
-          pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
-          pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
-          pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
+          pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
+          pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
+          pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
+          pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
+          pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
+          pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
+          pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
 
           // insert new TAG/PTE value into data TLB
           cpu->dtb->insert(val, pte);
       }
         break;
 
-      case ISA::IPR_ITB_PTE: {
-          struct ISA::PTE pte;
+      case TheISA::IPR_ITB_PTE: {
+          struct TheISA::PTE pte;
 
           // FIXME: granularity hints NYI...
           if (ITB_PTE_GH(val) != 0)
@@ -594,32 +598,32 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
           pte.fonr = ITB_PTE_FONR(val);
           pte.fonw = ITB_PTE_FONW(val);
           pte.asma = ITB_PTE_ASMA(val);
-          pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
+          pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
+          cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
       }
         break;
 
-      case ISA::IPR_ITB_IA:
+      case TheISA::IPR_ITB_IA:
         // really a control write
         ipr[idx] = 0;
 
         cpu->itb->flushAll();
         break;
 
-      case ISA::IPR_ITB_IAP:
+      case TheISA::IPR_ITB_IAP:
         // really a control write
         ipr[idx] = 0;
 
         cpu->itb->flushProcesses();
         break;
 
-      case ISA::IPR_ITB_IS:
+      case TheISA::IPR_ITB_IS:
         // really a control write
         ipr[idx] = val;
 
-        cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
+        cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
         break;
 
       default:
diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh
index a17ec7311..9781480b6 100644
--- a/cpu/o3/rename.hh
+++ b/cpu/o3/rename.hh
@@ -46,7 +46,6 @@ class SimpleRename
 {
   public:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::FullCPU FullCPU;
@@ -62,7 +61,8 @@ class SimpleRename
     typedef typename CPUPol::RenameMap RenameMap;
 
     // Typedefs from the ISA.
-    typedef typename ISA::Addr Addr;
+    typedef TheISA::Addr Addr;
+    typedef TheISA::RegIndex RegIndex;
 
   public:
     // Rename will block if ROB becomes full or issue queue becomes full,
diff --git a/cpu/o3/rename_map.hh b/cpu/o3/rename_map.hh
index c44c7a1ea..57be4a64a 100644
--- a/cpu/o3/rename_map.hh
+++ b/cpu/o3/rename_map.hh
@@ -38,9 +38,13 @@
 #include <vector>
 
 #include "cpu/o3/free_list.hh"
+//For RegIndex
+#include "arch/isa_traits.hh"
 
 class SimpleRenameMap
 {
+  protected:
+    typedef TheISA::RegIndex RegIndex;
   public:
     /**
      * Pair of a logical register and a physical register.  Tells the
diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh
index 29ec48007..1185564ad 100644
--- a/cpu/o3/rob.hh
+++ b/cpu/o3/rob.hh
@@ -47,6 +47,8 @@
 template <class Impl>
 class ROB
 {
+  protected:
+    typedef TheISA::RegIndex RegIndex;
   public:
     //Typedefs from the Impl.
     typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh
index bcd590384..c67d30fcb 100644
--- a/cpu/o3/store_set.hh
+++ b/cpu/o3/store_set.hh
@@ -31,11 +31,13 @@
 
 #include <vector>
 
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/inst_seq.hh"
 
 class StoreSet
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     typedef unsigned SSID;
 
diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh
index 58ea1a7d9..6cfd24cfb 100644
--- a/cpu/o3/tournament_pred.hh
+++ b/cpu/o3/tournament_pred.hh
@@ -30,11 +30,13 @@
 #define __CPU_O3_CPU_TOURNAMENT_PRED_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/o3/sat_counter.hh"
 
 class TournamentBP
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     /**
      * Default branch predictor constructor.
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 21fe05b6a..7976632d9 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -77,7 +77,6 @@ class OoOCPU : public BaseCPU
   private:
     typedef typename Impl::DynInst DynInst;
     typedef typename Impl::DynInstPtr DynInstPtr;
-    typedef typename Impl::ISA ISA;
 
   public:
     // main simulation loop (one cycle)
@@ -378,12 +377,12 @@ class OoOCPU : public BaseCPU
   private:
     InstSeqNum globalSeqNum;
 
-    DynInstPtr renameTable[ISA::TotalNumRegs];
-    DynInstPtr commitTable[ISA::TotalNumRegs];
+    DynInstPtr renameTable[TheISA::TotalNumRegs];
+    DynInstPtr commitTable[TheISA::TotalNumRegs];
 
     // Might need a table of the shadow registers as well.
 #if FULL_SYSTEM
-    DynInstPtr palShadowTable[ISA::NumIntRegs];
+    DynInstPtr palShadowTable[TheISA::NumIntRegs];
 #endif
 
   public:
@@ -402,47 +401,47 @@ class OoOCPU : public BaseCPU
     // rename table of DynInsts.  Also these likely shouldn't be called very
     // often, other than when adding things into the xc during say a syscall.
 
-    uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
+    uint64_t readIntReg(StaticInst *si, int idx)
     {
         return xc->readIntReg(si->srcRegIdx(idx));
     }
 
-    float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
+    float readFloatRegSingle(StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegSingle(reg_idx);
     }
 
-    double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
+    double readFloatRegDouble(StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegDouble(reg_idx);
     }
 
-    uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
+    uint64_t readFloatRegInt(StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegInt(reg_idx);
     }
 
-    void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
+    void setIntReg(StaticInst *si, int idx, uint64_t val)
     {
         xc->setIntReg(si->destRegIdx(idx), val);
     }
 
-    void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
+    void setFloatRegSingle(StaticInst *si, int idx, float val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegSingle(reg_idx, val);
     }
 
-    void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
+    void setFloatRegDouble(StaticInst *si, int idx, double val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegDouble(reg_idx, val);
     }
 
-    void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
+    void setFloatRegInt(StaticInst *si, int idx, uint64_t val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegInt(reg_idx, val);
@@ -479,7 +478,7 @@ class OoOCPU : public BaseCPU
     // We fold in the PISA 64- to 32-bit conversion here as well.
     Addr icacheBlockAlignPC(Addr addr)
     {
-        addr = ISA::realPCToFetchPC(addr);
+        addr = TheISA::realPCToFetchPC(addr);
         return (addr & ~(cacheBlkMask));
     }
 
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index 83fbc3e2d..7a294866d 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -136,14 +136,14 @@ BreakPCEvent::process(ExecContext *xc)
 #if FULL_SYSTEM
 extern "C"
 void
-sched_break_pc_sys(System *sys, Addr addr)
+sched_break_pc_sys(System *sys, TheISA::Addr addr)
 {
     new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
 }
 
 extern "C"
 void
-sched_break_pc(Addr addr)
+sched_break_pc(TheISA::Addr addr)
 {
      for (vector<System *>::iterator sysi = System::systemList.begin();
           sysi != System::systemList.end(); ++sysi) {
diff --git a/cpu/pc_event.hh b/cpu/pc_event.hh
index 7fa3902cc..3033a3cfd 100644
--- a/cpu/pc_event.hh
+++ b/cpu/pc_event.hh
@@ -39,6 +39,7 @@ class PCEventQueue;
 class PCEvent
 {
   protected:
+    typedef TheISA::Addr Addr;
     static const Addr badpc = MemReq::inval_addr;
 
   protected:
@@ -64,6 +65,7 @@ class PCEvent
 class PCEventQueue
 {
   protected:
+    typedef TheISA::Addr Addr;
     typedef PCEvent * record_t;
     class MapCompare {
       public:
@@ -132,6 +134,7 @@ PCEvent::remove()
 class BreakPCEvent : public PCEvent
 {
   protected:
+    typedef TheISA::Addr Addr;
     bool remove;
 
   public:
diff --git a/cpu/profile.hh b/cpu/profile.hh
index 58cd7e79f..b55f87a6a 100644
--- a/cpu/profile.hh
+++ b/cpu/profile.hh
@@ -37,6 +37,8 @@
 
 class ProfileNode
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     friend class FunctionProfile;
 
@@ -57,6 +59,8 @@ class ProfileNode
 class Callback;
 class FunctionProfile
 {
+  public:
+    typedef TheISA::Addr Addr;
   private:
     Callback *reset;
     const SymbolTable *symtab;
@@ -68,7 +72,7 @@ class FunctionProfile
     FunctionProfile(const SymbolTable *symtab);
     ~FunctionProfile();
 
-    ProfileNode *consume(ExecContext *xc, StaticInstPtr<TheISA> inst);
+    ProfileNode *consume(ExecContext *xc, StaticInstPtr inst);
     ProfileNode *consume(const std::vector<Addr> &stack);
     void clear();
     void dump(ExecContext *xc, std::ostream &out) const;
@@ -76,7 +80,7 @@ class FunctionProfile
 };
 
 inline ProfileNode *
-FunctionProfile::consume(ExecContext *xc, StaticInstPtr<TheISA> inst)
+FunctionProfile::consume(ExecContext *xc, StaticInstPtr inst)
 {
     if (!trace.trace(xc, inst))
         return NULL;
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 6aff94abd..c3f256de9 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -76,7 +76,7 @@
 
 using namespace std;
 //The SimpleCPU does alpha only
-using namespace LittleEndianGuest;
+using namespace AlphaISA;
 
 
 SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
@@ -125,7 +125,7 @@ SimpleCPU::SimpleCPU(Params *p)
     xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
 
     // initialize CPU, including PC
-    TheISA::initCPU(&xc->regs);
+    initCPU(&xc->regs);
 #else
     xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
 #endif // !FULL_SYSTEM
@@ -323,7 +323,7 @@ SimpleCPU::copySrcTranslate(Addr src)
 
     // Make sure block doesn't span page
     if (no_warn &&
-        (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
+        (src & PageMask) != ((src + blk_size) & PageMask) &&
         (src >> 40) != 0xfffffc) {
         warn("Copied block source spans pages %x.", src);
         no_warn = false;
@@ -359,7 +359,7 @@ SimpleCPU::copy(Addr dest)
 
     // Make sure block doesn't span page
     if (no_warn &&
-        (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
+        (dest & PageMask) != ((dest + blk_size) & PageMask) &&
         (dest >> 40) != 0xfffffc) {
         no_warn = false;
         warn("Copied block destination spans pages %x. ", dest);
@@ -648,20 +648,20 @@ SimpleCPU::tick()
         checkInterrupts = false;
         IntReg *ipr = xc->regs.ipr;
 
-        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
-            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
-                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
-                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
+        if (xc->regs.ipr[IPR_SIRR]) {
+            for (int i = INTLEVEL_SOFTWARE_MIN;
+                 i < INTLEVEL_SOFTWARE_MAX; i++) {
+                if (ipr[IPR_SIRR] & (ULL(1) << i)) {
                     // See table 4-19 of 21164 hardware reference
-                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
+                    ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                     summary |= (ULL(1) << i);
                 }
             }
         }
 
         uint64_t interrupts = xc->cpu->intr_status();
-        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
-            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
+        for (int i = INTLEVEL_EXTERNAL_MIN;
+            i < INTLEVEL_EXTERNAL_MAX; i++) {
             if (interrupts & (ULL(1) << i)) {
                 // See table 4-19 of 21164 hardware reference
                 ipl = i;
@@ -669,16 +669,16 @@ SimpleCPU::tick()
             }
         }
 
-        if (ipr[TheISA::IPR_ASTRR])
+        if (ipr[IPR_ASTRR])
             panic("asynchronous traps not implemented\n");
 
-        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
-            ipr[TheISA::IPR_ISR] = summary;
-            ipr[TheISA::IPR_INTID] = ipl;
+        if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
+            ipr[IPR_ISR] = summary;
+            ipr[IPR_INTID] = ipl;
             xc->ev5_trap(InterruptFault);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                    ipr[TheISA::IPR_IPLR], ipl, summary);
+                    ipr[IPR_IPLR], ipl, summary);
         }
     }
 #endif
@@ -749,7 +749,7 @@ SimpleCPU::tick()
 
         // decode the instruction
         inst = gtoh(inst);
-        curStaticInst = StaticInst<TheISA>::decode(inst);
+        curStaticInst = StaticInst::decode(inst);
 
         traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
                                          xc->regs.pc);
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index e7a447117..8a3900726 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -63,6 +63,8 @@ namespace Trace {
 
 class SimpleCPU : public BaseCPU
 {
+  protected:
+    typedef TheISA::MachInst MachInst;
   public:
     // main simulation loop (one cycle)
     void tick();
@@ -172,7 +174,7 @@ class SimpleCPU : public BaseCPU
     // the next switchover
     Sampler *sampler;
 
-    StaticInstPtr<TheISA> curStaticInst;
+    StaticInstPtr curStaticInst;
 
     class CacheCompletionEvent : public Event
     {
@@ -269,47 +271,47 @@ class SimpleCPU : public BaseCPU
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst<TheISA> *si, int idx)
+    uint64_t readIntReg(const StaticInst *si, int idx)
     {
         return xc->readIntReg(si->srcRegIdx(idx));
     }
 
-    float readFloatRegSingle(const StaticInst<TheISA> *si, int idx)
+    float readFloatRegSingle(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegSingle(reg_idx);
     }
 
-    double readFloatRegDouble(const StaticInst<TheISA> *si, int idx)
+    double readFloatRegDouble(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegDouble(reg_idx);
     }
 
-    uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx)
+    uint64_t readFloatRegInt(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegInt(reg_idx);
     }
 
-    void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val)
+    void setIntReg(const StaticInst *si, int idx, uint64_t val)
     {
         xc->setIntReg(si->destRegIdx(idx), val);
     }
 
-    void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val)
+    void setFloatRegSingle(const StaticInst *si, int idx, float val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegSingle(reg_idx, val);
     }
 
-    void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val)
+    void setFloatRegDouble(const StaticInst *si, int idx, double val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegDouble(reg_idx, val);
     }
 
-    void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val)
+    void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegInt(reg_idx, val);
diff --git a/cpu/static_inst.cc b/cpu/static_inst.cc
index 54bd9914e..c307dc6fc 100644
--- a/cpu/static_inst.cc
+++ b/cpu/static_inst.cc
@@ -30,19 +30,13 @@
 #include "cpu/static_inst.hh"
 #include "sim/root.hh"
 
-template <class ISA>
-StaticInstPtr<ISA> StaticInst<ISA>::nullStaticInstPtr;
-
-template <class ISA>
-typename StaticInst<ISA>::DecodeCache StaticInst<ISA>::decodeCache;
+StaticInstPtr StaticInst::nullStaticInstPtr;
 
 // Define the decode cache hash map.
-template StaticInst<AlphaISA>::DecodeCache
-StaticInst<AlphaISA>::decodeCache;
+StaticInst::DecodeCache StaticInst::decodeCache;
 
-template <class ISA>
 void
-StaticInst<ISA>::dumpDecodeCacheStats()
+StaticInst::dumpDecodeCacheStats()
 {
     using namespace std;
 
@@ -62,13 +56,8 @@ StaticInst<ISA>::dumpDecodeCacheStats()
     }
 }
 
-
-template StaticInstPtr<AlphaISA>
-StaticInst<AlphaISA>::nullStaticInstPtr;
-
-template <class ISA>
 bool
-StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
+StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
 {
     if (isDirectCtrl()) {
         tgt = branchTarget(pc);
@@ -83,6 +72,3 @@ StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
     return false;
 }
 
-
-// force instantiation of template function(s) above
-template class StaticInst<AlphaISA>;
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index c574173c2..333a6f1ca 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -214,7 +214,6 @@ class StaticInstBase : public RefCounted
 
 
 // forward declaration
-template <class ISA>
 class StaticInstPtr;
 
 /**
@@ -224,21 +223,20 @@ class StaticInstPtr;
  * that are generic across all ISAs but that differ in details
  * according to the specific ISA being used.
  */
-template <class ISA>
 class StaticInst : public StaticInstBase
 {
   public:
 
     /// Binary machine instruction type.
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
     /// Memory address type.
-    typedef typename ISA::Addr	   Addr;
+    typedef TheISA::Addr	   Addr;
     /// Logical register index type.
-    typedef typename ISA::RegIndex RegIndex;
+    typedef TheISA::RegIndex RegIndex;
 
     enum {
-        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
-        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
+        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
     };
 
 
@@ -253,7 +251,7 @@ class StaticInst : public StaticInstBase
     /// Pointer to a statically allocated "null" instruction object.
     /// Used to give eaCompInst() and memAccInst() something to return
     /// when called on non-memory instructions.
-    static StaticInstPtr<ISA> nullStaticInstPtr;
+    static StaticInstPtr nullStaticInstPtr;
 
     /**
      * Memory references only: returns "fake" instruction representing
@@ -262,7 +260,7 @@ class StaticInst : public StaticInstBase
      * just the EA computation.
      */
     virtual const
-    StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
+    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 
     /**
      * Memory references only: returns "fake" instruction representing
@@ -271,7 +269,7 @@ class StaticInst : public StaticInstBase
      * just the memory access (not the EA computation).
      */
     virtual const
-    StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
+    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 
     /// The binary machine instruction.
     const MachInst machInst;
@@ -370,7 +368,7 @@ class StaticInst : public StaticInstBase
     /// Decoded instruction cache type.
     /// For now we're using a generic hash_map; this seems to work
     /// pretty well.
-    typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
+    typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache;
 
     /// A cache of decoded instruction objects.
     static DecodeCache decodeCache;
@@ -384,63 +382,40 @@ class StaticInst : public StaticInstBase
     /// Decode a machine instruction.
     /// @param mach_inst The binary instruction to decode.
     /// @retval A pointer to the corresponding StaticInst object.
-    static
-    StaticInstPtr<ISA> decode(MachInst mach_inst)
-    {
-#ifdef DECODE_CACHE_HASH_STATS
-        // Simple stats on decode hash_map.  Turns out the default
-        // hash function is as good as anything I could come up with.
-        const int dump_every_n = 10000000;
-        static int decodes_til_dump = dump_every_n;
-
-        if (--decodes_til_dump == 0) {
-            dumpDecodeCacheStats();
-            decodes_til_dump = dump_every_n;
-        }
-#endif
-
-        typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
-        if (iter != decodeCache.end()) {
-            return iter->second;
-        }
-
-        StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
-        decodeCache[mach_inst] = si;
-        return si;
-    }
+    //This is defined as inline below.
+    static StaticInstPtr decode(MachInst mach_inst);
 };
 
 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 
 /// Reference-counted pointer to a StaticInst object.
-/// This type should be used instead of "StaticInst<ISA> *" so that
+/// This type should be used instead of "StaticInst *" so that
 /// StaticInst objects can be properly reference-counted.
-template <class ISA>
-class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
+class StaticInstPtr : public RefCountingPtr<StaticInst>
 {
   public:
     /// Constructor.
     StaticInstPtr()
-        : RefCountingPtr<StaticInst<ISA> >()
+        : RefCountingPtr<StaticInst>()
     {
     }
 
-    /// Conversion from "StaticInst<ISA> *".
-    StaticInstPtr(StaticInst<ISA> *p)
-        : RefCountingPtr<StaticInst<ISA> >(p)
+    /// Conversion from "StaticInst *".
+    StaticInstPtr(StaticInst *p)
+        : RefCountingPtr<StaticInst>(p)
     {
     }
 
     /// Copy constructor.
     StaticInstPtr(const StaticInstPtr &r)
-        : RefCountingPtr<StaticInst<ISA> >(r)
+        : RefCountingPtr<StaticInst>(r)
     {
     }
 
     /// Construct directly from machine instruction.
-    /// Calls StaticInst<ISA>::decode().
-    StaticInstPtr(typename ISA::MachInst mach_inst)
-        : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
+    /// Calls StaticInst::decode().
+    StaticInstPtr(TheISA::MachInst mach_inst)
+        : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
     {
     }
 
@@ -451,4 +426,29 @@ class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
     }
 };
 
+inline StaticInstPtr
+StaticInst::decode(StaticInst::MachInst mach_inst)
+{
+#ifdef DECODE_CACHE_HASH_STATS
+    // Simple stats on decode hash_map.  Turns out the default
+    // hash function is as good as anything I could come up with.
+    const int dump_every_n = 10000000;
+    static int decodes_til_dump = dump_every_n;
+
+    if (--decodes_til_dump == 0) {
+        dumpDecodeCacheStats();
+        decodes_til_dump = dump_every_n;
+    }
+#endif
+
+    DecodeCache::iterator iter = decodeCache.find(mach_inst);
+    if (iter != decodeCache.end()) {
+        return iter->second;
+    }
+
+    StaticInstPtr si = TheISA::decodeInst(mach_inst);
+    decodeCache[mach_inst] = si;
+    return si;
+}
+
 #endif // __CPU_STATIC_INST_HH__
diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh
index f81691733..704dc09fa 100644
--- a/cpu/trace/opt_cpu.hh
+++ b/cpu/trace/opt_cpu.hh
@@ -49,6 +49,8 @@ class MemTraceReader;
  */
 class OptCPU : public SimObject
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     typedef int RefIndex;
 
diff --git a/cpu/trace/reader/itx_reader.hh b/cpu/trace/reader/itx_reader.hh
index faec73138..e402b2d52 100644
--- a/cpu/trace/reader/itx_reader.hh
+++ b/cpu/trace/reader/itx_reader.hh
@@ -46,6 +46,9 @@
  */
 class ITXReader : public MemTraceReader
 {
+  protected:
+    typedef TheISA::Addr Addr;
+  private:
     /** Trace file. */
     FILE *trace;
 
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 38fbbdef0..a7ef8f641 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -53,6 +53,7 @@
 #include "sim/system.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
                            System *s, BaseCPU *c, Platform *p,
diff --git a/dev/baddev.cc b/dev/baddev.cc
index b6ca919e4..62871e348 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -46,6 +46,7 @@
 #include "sim/system.hh"
 
 using namespace std;
+using namespace TheISA;
 
 BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
                      HierParams *hier, Bus *pio_bus, const string &devicename)
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index a5cb0dfd8..18c988b81 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -48,6 +48,7 @@
 #include "sim/sim_object.hh"
 
 using namespace std;
+using namespace TheISA;
 
 ////
 // Initialization and destruction
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index 9d8bb8825..41400c590 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -53,6 +53,7 @@
 #include "arch/isa_traits.hh"
 
 using namespace std;
+using namespace TheISA;
 
 IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
                  int id, Tick delay)
diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh
index a656ca464..32888c81c 100644
--- a/dev/ide_disk.hh
+++ b/dev/ide_disk.hh
@@ -188,6 +188,8 @@ class IdeController;
 class IdeDisk : public SimObject
 {
   protected:
+    typedef TheISA::Addr Addr;
+  protected:
     /** The IDE controller for this disk. */
     IdeController *ctrl;
     /** The DMA interface to use for transfers */
diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc
index 93c9eedbf..117c9e5ad 100644
--- a/dev/isa_fake.cc
+++ b/dev/isa_fake.cc
@@ -45,6 +45,7 @@
 #include "sim/system.hh"
 
 using namespace std;
+using namespace TheISA;
 
 IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
                          HierParams *hier, Bus *pio_bus, Addr size)
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index c28615438..07bf178fc 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -84,6 +84,7 @@ const char *NsDmaState[] =
 
 using namespace std;
 using namespace Net;
+using namespace TheISA;
 
 ///////////////////////////////////////////////////////////////////////
 //
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index 1175172c4..c581e1561 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -47,6 +47,7 @@
 #include "sim/system.hh"
 
 using namespace std;
+using namespace TheISA;
 
 PciConfigAll::PciConfigAll(const string &name,
                            Addr a, MemoryController *mmu,
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index c8d9685c1..a100bf746 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -53,6 +53,8 @@ class MemoryController;
  */
 class PciConfigData : public SimObject
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     /**
      * Constructor to initialize the devices config space to 0.
diff --git a/dev/platform.cc b/dev/platform.cc
index 58f94db7b..5b667b12c 100644
--- a/dev/platform.cc
+++ b/dev/platform.cc
@@ -31,6 +31,7 @@
 #include "sim/sim_exit.hh"
 
 using namespace std;
+using namespace TheISA;
 
 Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci)
     : SimObject(name), intrctrl(intctrl), pciconfig(pci)
diff --git a/dev/platform.hh b/dev/platform.hh
index 1ee645454..87810250a 100644
--- a/dev/platform.hh
+++ b/dev/platform.hh
@@ -44,6 +44,8 @@ class Uart;
 
 class Platform : public SimObject
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     /** Pointer to the interrupt controller */
     IntrControl *intrctrl;
diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh
index 6560e15c2..f68d5bfff 100644
--- a/dev/simple_disk.hh
+++ b/dev/simple_disk.hh
@@ -44,19 +44,21 @@ class PhysicalMemory;
  */
 class SimpleDisk : public SimObject
 {
-public:
-  typedef uint64_t baddr_t;
+  protected:
+    typedef TheISA::Addr Addr;
+  public:
+    typedef uint64_t baddr_t;
 
-protected:
-  PhysicalMemory  *physmem;
-  DiskImage *image;
+  protected:
+    PhysicalMemory  *physmem;
+    DiskImage *image;
 
-public:
-  SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
-  ~SimpleDisk();
+  public:
+    SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
+    ~SimpleDisk();
 
-  void read(Addr addr, baddr_t block, int count) const;
-  void write(Addr addr, baddr_t block, int count);
+    void read(Addr addr, baddr_t block, int count) const;
+    void write(Addr addr, baddr_t block, int count);
 };
 
 #endif // __DEV_SIMPLE_DISK_HH__
diff --git a/dev/sinic.cc b/dev/sinic.cc
index e79f80678..829d58d32 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -50,6 +50,7 @@
 #include "targetarch/vtophys.hh"
 
 using namespace Net;
+using namespace TheISA;
 
 namespace Sinic {
 
diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh
index b7008b4e1..343db6303 100644
--- a/dev/sinicreg.hh
+++ b/dev/sinicreg.hh
@@ -165,7 +165,7 @@ struct Info
 /* namespace Regs */ }
 
 inline const Regs::Info&
-regInfo(Addr daddr)
+regInfo(TheISA::Addr daddr)
 {
     static Regs::Info invalid = { 0, false, false, false, false, "invalid" };
     static Regs::Info info [] = {
@@ -201,7 +201,7 @@ regInfo(Addr daddr)
 }
 
 inline bool
-regValid(Addr daddr)
+regValid(TheISA::Addr daddr)
 {
     if (daddr > Regs::Size)
         return false;
diff --git a/dev/tsunami.cc b/dev/tsunami.cc
index 760848a00..58fc7434e 100644
--- a/dev/tsunami.cc
+++ b/dev/tsunami.cc
@@ -46,6 +46,8 @@
 #include "sim/system.hh"
 
 using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
 
 Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
                  PciConfigAll *pci)
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index 7fd91d5b2..79b561ed7 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -55,6 +55,8 @@ class System;
 
 class Tsunami : public Platform
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     /** Max number of CPUs in a Tsunami */
     static const int Max_CPUs = 64;
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 4cda9ec36..10c08a7a2 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -47,6 +47,8 @@
 #include "sim/system.hh"
 
 using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
 
 TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
                            MemoryController *mmu, HierParams *hier,
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 0d0d27570..e90bb5abc 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -50,6 +50,8 @@
 #include "mem/functional/memory_control.hh"
 
 using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
 
 TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i)
     : _name(name), event(t, i), addr(0)
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index a4c04a79f..706daf9dc 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -47,6 +47,8 @@
 #include "sim/system.hh"
 
 using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
 
 TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
                            MemoryController *mmu, HierParams *hier,
diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index a2e782189..99355e28a 100644
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -46,6 +46,7 @@
 #include "sim/builder.hh"
 
 using namespace std;
+using namespace TheISA;
 
 Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
     : Event(&mainEventQueue), uart(u)
diff --git a/kern/freebsd/freebsd_system.cc b/kern/freebsd/freebsd_system.cc
index dbf60a3fc..cead8caaf 100644
--- a/kern/freebsd/freebsd_system.cc
+++ b/kern/freebsd/freebsd_system.cc
@@ -46,6 +46,7 @@
 #define TIMER_FREQUENCY 1193180
 
 using namespace std;
+using namespace TheISA;
 
 FreebsdSystem::FreebsdSystem(Params *p)
     : System(p)
diff --git a/kern/kernel_stats.hh b/kern/kernel_stats.hh
index 98cc044ac..e4d5ec011 100644
--- a/kern/kernel_stats.hh
+++ b/kern/kernel_stats.hh
@@ -50,6 +50,8 @@ extern const char *modestr[];
 
 class Binning
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     std::string myname;
     System *system;
@@ -106,7 +108,7 @@ class Binning
 
     cpu_mode themode;
     void palSwapContext(ExecContext *xc);
-    void execute(ExecContext *xc, StaticInstPtr<TheISA> inst);
+    void execute(ExecContext *xc, StaticInstPtr inst);
     void call(ExecContext *xc, Stats::MainBin *myBin);
     void changeMode(cpu_mode mode);
 
@@ -124,6 +126,9 @@ class Binning
 
 class Statistics : public Serializable
 {
+  protected:
+    typedef TheISA::Addr Addr;
+  private:
     friend class Binning;
 
   private:
diff --git a/kern/linux/aligned.hh b/kern/linux/aligned.hh
index 18d1b43c0..137f65076 100644
--- a/kern/linux/aligned.hh
+++ b/kern/linux/aligned.hh
@@ -37,7 +37,7 @@
 #if __GNUC__ == 3 && __GNUC_MINOR__  != 3
 typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ;
 typedef int64_t int64_ta __attribute__ ((aligned (8))) ;
-typedef Addr Addr_a __attribute__ ((aligned (8))) ;
+typedef TheISA::Addr Addr_a __attribute__ ((aligned (8))) ;
 #else
 #define uint64_ta uint64_t __attribute__ ((aligned (8)))
 #define int64_ta int64_t __attribute__ ((aligned (8)))
diff --git a/kern/linux/linux_system.cc b/kern/linux/linux_system.cc
index 26a4c0d3e..c5a9e184a 100644
--- a/kern/linux/linux_system.cc
+++ b/kern/linux/linux_system.cc
@@ -50,6 +50,7 @@
 #include "targetarch/vtophys.hh"
 
 using namespace std;
+using namespace TheISA;
 
 LinuxSystem::LinuxSystem(Params *p)
     : System(p)
diff --git a/kern/linux/linux_threadinfo.hh b/kern/linux/linux_threadinfo.hh
index 9bab1dc49..f20188360 100644
--- a/kern/linux/linux_threadinfo.hh
+++ b/kern/linux/linux_threadinfo.hh
@@ -37,6 +37,8 @@ namespace Linux {
 
 class ThreadInfo
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     ExecContext *xc;
 
@@ -53,7 +55,7 @@ class ThreadInfo
          * thread_info struct. So we can get the address by masking off
          * the lower 14 bits.
          */
-        current = xc->regs.intRegFile[StackPointerReg] & ~0x3fff;
+        current = xc->regs.intRegFile[TheISA::StackPointerReg] & ~0x3fff;
         return VPtr<thread_info>(xc, current);
     }
 
diff --git a/kern/system_events.cc b/kern/system_events.cc
index ba3c9274a..55595b9b6 100644
--- a/kern/system_events.cc
+++ b/kern/system_events.cc
@@ -29,6 +29,8 @@
 #include "encumbered/cpu/full/cpu.hh"
 #include "kern/kernel_stats.hh"
 
+using namespace TheISA;
+
 void
 SkipFuncEvent::process(ExecContext *xc)
 {
diff --git a/kern/tru64/dump_mbuf.cc b/kern/tru64/dump_mbuf.cc
index 85cb4de96..efdaed62d 100644
--- a/kern/tru64/dump_mbuf.cc
+++ b/kern/tru64/dump_mbuf.cc
@@ -38,6 +38,8 @@
 #include "arch/isa_traits.hh"
 #include "targetarch/vtophys.hh"
 
+using namespace TheISA;
+
 namespace tru64 {
 
 void
diff --git a/kern/tru64/mbuf.hh b/kern/tru64/mbuf.hh
index 93424858f..7b84b5e10 100644
--- a/kern/tru64/mbuf.hh
+++ b/kern/tru64/mbuf.hh
@@ -35,35 +35,35 @@
 namespace tru64 {
 
 struct m_hdr {
-    Addr	mh_next;	// 0x00
-    Addr	mh_nextpkt;	// 0x08
-    Addr	mh_data;	// 0x10
+    TheISA::Addr	mh_next;	// 0x00
+    TheISA::Addr	mh_nextpkt;	// 0x08
+    TheISA::Addr	mh_data;	// 0x10
     int32_t	mh_len;		// 0x18
     int32_t	mh_type;	// 0x1C
     int32_t	mh_flags;	// 0x20
     int32_t	mh_pad0;	// 0x24
-    Addr	mh_foo[4];	// 0x28, 0x30, 0x38, 0x40
+    TheISA::Addr	mh_foo[4];	// 0x28, 0x30, 0x38, 0x40
 };
 
 struct	pkthdr {
     int32_t	len;
     int32_t	protocolSum;
-    Addr	rcvif;
+    TheISA::Addr	rcvif;
 };
 
 struct m_ext {
-    Addr	ext_buf;	// 0x00
-    Addr	ext_free;	// 0x08
+    TheISA::Addr	ext_buf;	// 0x00
+    TheISA::Addr	ext_free;	// 0x08
     uint32_t	ext_size;	// 0x10
     uint32_t	ext_pad0;	// 0x14
-    Addr	ext_arg;	// 0x18
+    TheISA::Addr	ext_arg;	// 0x18
     struct	ext_refq {
-        Addr	forw, back;	// 0x20, 0x28
+        TheISA::Addr	forw, back;	// 0x20, 0x28
     } ext_ref;
-    Addr	uiomove_f;	// 0x30
+    TheISA::Addr	uiomove_f;	// 0x30
     int32_t	protocolSum;	// 0x38
     int32_t	bytesSummed;	// 0x3C
-    Addr	checksum;	// 0x40
+    TheISA::Addr	checksum;	// 0x40
 };
 
 struct mbuf {
diff --git a/kern/tru64/tru64_events.cc b/kern/tru64/tru64_events.cc
index d769aab0f..2fe6a2dc4 100644
--- a/kern/tru64/tru64_events.cc
+++ b/kern/tru64/tru64_events.cc
@@ -36,6 +36,8 @@
 #include "targetarch/arguments.hh"
 #include "arch/isa_traits.hh"
 
+using namespace TheISA;
+
 //void SkipFuncEvent::process(ExecContext *xc);
 
 void
diff --git a/sim/process.cc b/sim/process.cc
index 59d122b48..b2f3046fb 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -53,6 +53,7 @@
 #endif
 
 using namespace std;
+using namespace TheISA;
 
 //
 // The purpose of this code is to fake the loader & syscall mechanism
diff --git a/sim/process.hh b/sim/process.hh
index 43fafd9d7..f5b713e3c 100644
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -50,6 +50,10 @@ class ExecContext;
 class FunctionalMemory;
 class Process : public SimObject
 {
+  protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::RegFile RegFile;
+    typedef TheISA::MachInst MachInst;
   public:
 
     // have we initialized an execution context from this process?  If
diff --git a/sim/pseudo_inst.cc b/sim/pseudo_inst.cc
index 11ab55f53..58ea8266f 100644
--- a/sim/pseudo_inst.cc
+++ b/sim/pseudo_inst.cc
@@ -53,6 +53,7 @@ using namespace std;
 extern Sampler *SampCPU;
 
 using namespace Stats;
+using namespace TheISA;
 
 namespace AlphaPseudo
 {
diff --git a/sim/pseudo_inst.hh b/sim/pseudo_inst.hh
index 3857f2050..07bdd7091 100644
--- a/sim/pseudo_inst.hh
+++ b/sim/pseudo_inst.hh
@@ -52,8 +52,8 @@ namespace AlphaPseudo
     void dumpstats(ExecContext *xc, Tick delay, Tick period);
     void dumpresetstats(ExecContext *xc, Tick delay, Tick period);
     void m5checkpoint(ExecContext *xc, Tick delay, Tick period);
-    uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset);
+    uint64_t readfile(ExecContext *xc, TheISA::Addr vaddr, uint64_t len, uint64_t offset);
     void debugbreak(ExecContext *xc);
     void switchcpu(ExecContext *xc);
-    void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr);
+    void addsymbol(ExecContext *xc, TheISA::Addr addr, TheISA::Addr symbolAddr);
 }
diff --git a/sim/syscall_emul.cc b/sim/syscall_emul.cc
index 0fac43fc5..68001b0d1 100644
--- a/sim/syscall_emul.cc
+++ b/sim/syscall_emul.cc
@@ -40,6 +40,7 @@
 #include "sim/sim_events.hh"
 
 using namespace std;
+using namespace TheISA;
 
 void
 SyscallDesc::doSyscall(int callnum, Process *process, ExecContext *xc)
@@ -89,7 +90,7 @@ exitFunc(SyscallDesc *desc, int callnum, Process *process,
 SyscallReturn
 getpagesizeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
 {
-    return VMPageSize;
+    return (int)VMPageSize;
 }
 
 
diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh
index 739cd20e5..bc22c5c4c 100644
--- a/sim/syscall_emul.hh
+++ b/sim/syscall_emul.hh
@@ -90,6 +90,9 @@ class SyscallDesc {
 
 class BaseBufferArg {
 
+  protected:
+    typedef TheISA::Addr Addr;
+
   public:
 
     BaseBufferArg(Addr _addr, int _size) : addr(_addr), size(_size)
@@ -636,7 +639,7 @@ template <class OS>
 SyscallReturn
 mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
 {
-    Addr start = xc->getSyscallArg(0);
+    TheISA::Addr start = xc->getSyscallArg(0);
     uint64_t length = xc->getSyscallArg(1);
     // int prot = xc->getSyscallArg(2);
     int flags = xc->getSyscallArg(3);
@@ -646,7 +649,7 @@ mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
     if (start == 0) {
         // user didn't give an address... pick one from our "mmap region"
         start = p->mmap_end;
-        p->mmap_end += roundUp(length, VMPageSize);
+        p->mmap_end += roundUp(length, TheISA::VMPageSize);
         if (p->nxm_start != 0) {
             //If we have an nxm space, make sure we haven't colided
             assert(p->mmap_end < p->nxm_start);
diff --git a/sim/system.cc b/sim/system.cc
index 990145826..ebeb5b244 100644
--- a/sim/system.cc
+++ b/sim/system.cc
@@ -41,6 +41,7 @@
 #include "base/trace.hh"
 
 using namespace std;
+using namespace TheISA;
 
 vector<System *> System::systemList;
 
diff --git a/sim/system.hh b/sim/system.hh
index aa697c040..4bf33a170 100644
--- a/sim/system.hh
+++ b/sim/system.hh
@@ -50,6 +50,8 @@ namespace Kernel { class Binning; }
 
 class System : public SimObject
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     MemoryController *memctrl;
     PhysicalMemory *physmem;
diff --git a/sim/vptr.hh b/sim/vptr.hh
index 7ec43602d..1baa00610 100644
--- a/sim/vptr.hh
+++ b/sim/vptr.hh
@@ -37,6 +37,8 @@ class ExecContext;
 template <class T>
 class VPtr
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     typedef T Type;