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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-11-12 22:03:42 -0800 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-11-12 22:03:42 -0800 |
commit | 0f633c5fee2a371bc216ca71192c6ff02dcc3b5c (patch) | |
tree | 47ef3020fc458c9a14bcd819847c3f7481390ebf | |
parent | d2d44317528ffadf81fbb95c92291d8d2d4a2190 (diff) | |
download | gem5-0f633c5fee2a371bc216ca71192c6ff02dcc3b5c.tar.xz |
Make setRegWithEffect do something in SE mode.
--HG--
extra : convert_revision : 88fdaa403fe6d083f8c8fc064cb0d0d6a8b8daf8
-rw-r--r-- | src/arch/alpha/miscregfile.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 4cf57a690..962d4609f 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -132,7 +132,6 @@ namespace AlphaISA MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val, ThreadContext *tc) { -#if FULL_SYSTEM switch(misc_reg) { case MISCREG_FPCR: fpcr = val; @@ -150,12 +149,13 @@ namespace AlphaISA intr_flag = val; return; default: - return setIpr(misc_reg, val, tc); - } +#if FULL_SYSTEM + setIpr(misc_reg, val, tc); #else - //panic("No registers with side effects in SE mode!"); - return; + panic("No registers with side effects in SE mode!"); #endif + return; + } } } |