use string name to figure out if we have a "AndLink" instruction

arch/mips/isa/operands.isa:
    uq -> uw

--HG--
extra : convert_revision : eeac6dba813de8174d080a5fa9b5a396b345113a

2 files changed, 9 insertions, 7 deletions

diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index 75e7830d0..c003cb63d 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -213,10 +213,11 @@ def template JumpOrBranchDecode {{
 }};
 
 def format Branch(code,*flags) {{
-    code = 'bool cond;\n' + code + '\n'
+    code = 'bool cond;\n\t' + code + '\n'
 
-    if flags == 'IsLink':
-        code += 'R31 = NPC + 8\n'
+    strlen = len(name)
+    if name[strlen-2:] == 'al':
+        code += 'R31 = NPC + 8;\n'
 
     code += '\nif (cond) NPC = NPC + disp;\n';
 
@@ -231,8 +232,9 @@ def format Branch(code,*flags) {{
 def format BranchLikely(code,*flags) {{
     code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
 
-    if flags == 'IsLink':
-        code += 'R31 = NPC + 8\n'
+    strlen = len(name)
+    if name[strlen-3:] == 'all':
+        code += 'R31 = NPC + 8;\n'
 
     iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
                         ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index cf6f10e0b..19d21ac8d 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -26,10 +26,10 @@ def operands {{
 
     'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
 
-    #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
+    #'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
     #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
     #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     #'R0':  ('IntReg', 'uq', '0', None, 1),
-    #'R16': ('IntReg', 'uq', '16', None, 1)
+    #'R31': ('IntReg', 'uw', '31', None, 1)
 }};