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authorKorey Sewell <ksewell@umich.edu>2010-06-23 18:15:23 -0400
committerKorey Sewell <ksewell@umich.edu>2010-06-23 18:15:23 -0400
commit39ac4dce04ccf2d83a29fcd7fc698f607bf720d4 (patch)
treedfff805e6c3de9db90c918bd39bd02a3c4d4535d
parent7695d4c63fb702ae9d53285f8e544c6c7c13fa74 (diff)
downloadgem5-39ac4dce04ccf2d83a29fcd7fc698f607bf720d4.tar.xz
inorder: stall signal handling
remove stall only when necessary add debugging printfs
-rw-r--r--src/cpu/inorder/pipeline_stage.cc22
1 files changed, 19 insertions, 3 deletions
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index dcf4d81bf..deed695eb 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -233,8 +233,21 @@ PipelineStage::checkStall(ThreadID tid) const
void
PipelineStage::removeStalls(ThreadID tid)
{
- for (int stNum = 0; stNum < NumStages; stNum++) {
- stalls[tid].stage[stNum] = false;
+ for (int st_num = 0; st_num < NumStages; st_num++) {
+ if (stalls[tid].stage[st_num] == true) {
+ DPRINTF(InOrderStage, "Removing stall from stage %i.\n", st_num);
+ stalls[tid].stage[st_num] = false;
+ }
+
+ if (toPrevStages->stageBlock[st_num][tid] == true) {
+ DPRINTF(InOrderStage, "Removing pending block from stage %i.\n", st_num);
+ toPrevStages->stageBlock[st_num][tid] = false;
+ }
+
+ if (fromNextStages->stageBlock[st_num][tid] == true) {
+ DPRINTF(InOrderStage, "Removing pending block from stage %i.\n", st_num);
+ fromNextStages->stageBlock[st_num][tid] = false;
+ }
}
stalls[tid].resources.clear();
}
@@ -626,12 +639,15 @@ PipelineStage::readStallSignals(ThreadID tid)
// Check for Stage Blocking Signal
if (fromNextStages->stageBlock[stage_idx][tid]) {
+ DPRINTF(InOrderStage, "[tid:%i] Stall from stage %i set.\n", tid,
+ stage_idx);
stalls[tid].stage[stage_idx] = true;
}
// Check for Stage Unblocking Signal
if (fromNextStages->stageUnblock[stage_idx][tid]) {
- //assert(fromNextStages->stageBlock[stage_idx][tid]);
+ DPRINTF(InOrderStage, "[tid:%i] Stall from stage %i unset.\n", tid,
+ stage_idx);
stalls[tid].stage[stage_idx] = false;
}
}