Registers: Move the PCs out of the ISAs and into the CPUs.

15 files changed, 73 insertions, 385 deletions

diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index 9a9ac41a7..15df83859 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -55,8 +55,6 @@ const int reg_redir[NumIntRegs] = {
 void
 RegFile::serialize(EventManager *em, ostream &os)
 {
-    SERIALIZE_SCALAR(pc);
-    SERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
     SERIALIZE_SCALAR(intrflag);
 #endif
@@ -65,8 +63,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 void
 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
-    UNSERIALIZE_SCALAR(pc);
-    UNSERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
     UNSERIALIZE_SCALAR(intrflag);
 #endif
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index accb06302..39c56e57a 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -32,10 +32,6 @@
 #define __ARCH_ALPHA_REGFILE_HH__
 
 #include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/miscregfile.hh"
-#include "arch/alpha/types.hh"
-#include "arch/alpha/mt.hh"
-#include "sim/faults.hh"
 
 #include <string>
 
@@ -51,46 +47,6 @@ namespace AlphaISA {
 extern const int reg_redir[NumIntRegs];
 
 class RegFile {
-  protected:
-    Addr pc;   // program counter
-    Addr npc;  // next-cycle program counter
-    Addr nnpc; // next next-cycle program counter
-
-  public:
-    Addr
-    readPC()
-    {
-        return pc;
-    }
-
-    void
-    setPC(Addr val)
-    {
-        pc = val;
-    }
-
-    Addr
-    readNextPC()
-    {
-        return npc;
-    }
-
-    void
-    setNextPC(Addr val)
-    {
-        npc = val;
-    }
-
-    Addr
-    readNextNPC()
-    {
-        return npc + sizeof(MachInst);
-    }
-
-    void
-    setNextNPC(Addr val)
-    { }
-
   public:
 #if FULL_SYSTEM
     int intrflag;                   // interrupt flag
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
index a0365e3d3..2d995df93 100644
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -55,18 +55,4 @@ MiscRegFile::copyMiscRegs(ThreadContext *tc)
     panic("Copy Misc. Regs Not Implemented Yet\n");
 }
 
-void
-RegFile::serialize(EventManager *em, ostream &os)
-{
-    SERIALIZE_SCALAR(npc);
-    SERIALIZE_SCALAR(nnpc);
-}
-
-void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
-{
-    UNSERIALIZE_SCALAR(npc);
-    UNSERIALIZE_SCALAR(nnpc);
-}
-
 } // namespace ArmISA
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
index 69d4252a6..cd2d4ee2c 100644
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -99,46 +99,12 @@ namespace ArmISA
 
         void clear()
         {}
-      protected:
 
-        Addr pc;			// program counter
-        Addr npc;			// next-cycle program counter
-        Addr nnpc;			// next-next-cycle program counter
-
-      public:
-        Addr readPC()
-        {
-            return pc;
-        }
-
-        void setPC(Addr val)
-        {
-            pc = val;
-        }
-
-        Addr readNextPC()
-        {
-            return npc;
-        }
-
-        void setNextPC(Addr val)
-        {
-            npc = val;
-        }
-
-        Addr readNextNPC()
-        {
-            return npc + sizeof(MachInst);
-        }
-
-        void setNextNPC(Addr val)
-        {
-            //nnpc = val;
-        }
-
-        void serialize(EventManager *em, std::ostream &os);
+        void serialize(EventManager *em, std::ostream &os)
+        {}
         void unserialize(EventManager *em, Checkpoint *cp,
-                         const std::string &section);
+                         const std::string &section)
+        {}
     };
 
     void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 0b5f10611..7b54b853d 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -36,7 +36,6 @@ if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
     Source('isa.cc')
     Source('regfile/misc_regfile.cc')
-    Source('regfile/regfile.cc')
     Source('tlb.cc')
     Source('pagetable.cc')
     Source('utility.cc')
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
deleted file mode 100644
index a19962ff3..000000000
--- a/src/arch/mips/regfile/regfile.cc
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Korey Sewell
- */
-
-#include "arch/mips/regfile/regfile.hh"
-#include "sim/serialize.hh"
-
-using namespace std;
-
-namespace MipsISA
-{
-
-void
-RegFile::clear()
-{
-}
-
-void
-RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
-               BaseCPU *_cpu)
-{
-}
-
-void
-RegFile::setShadowSet(int css){
-}
-
-
-Addr
-RegFile::readPC()
-{
-    return pc;
-}
-
-void
-RegFile::setPC(Addr val)
-{
-    pc = val;
-}
-
-Addr
-RegFile::readNextPC()
-{
-    return npc;
-}
-
-void
-RegFile::setNextPC(Addr val)
-{
-    npc = val;
-}
-
-Addr
-RegFile::readNextNPC()
-{
-    return nnpc;
-}
-
-void
-RegFile::setNextNPC(Addr val)
-{
-    nnpc = val;
-}
-
-void
-RegFile::serialize(EventManager *em, std::ostream &os)
-{
-    SERIALIZE_SCALAR(pc);
-    SERIALIZE_SCALAR(npc);
-    SERIALIZE_SCALAR(nnpc);
-}
-
-void
-RegFile::unserialize(EventManager *em, Checkpoint *cp,
-    const std::string &section)
-{
-    UNSERIALIZE_SCALAR(pc);
-    UNSERIALIZE_SCALAR(npc);
-    UNSERIALIZE_SCALAR(nnpc);
-}
-
-} // namespace MipsISA
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 28d295022..71775edc4 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -32,11 +32,10 @@
 #ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__
 #define __ARCH_MIPS_REGFILE_REGFILE_HH__
 
-#include "arch/mips/types.hh"
+#include <iostream>
+#include <string>
+
 #include "arch/mips/isa_traits.hh"
-//#include "arch/mips/mt.hh"
-//#include "cpu/base.hh"
-#include "sim/faults.hh"
 
 class BaseCPU;
 class Checkpoint;
@@ -95,33 +94,22 @@ namespace MipsISA
 
 
     class RegFile {
-      protected:
-        Addr pc;                        // program counter
-        Addr npc;                       // next-cycle program counter
-        Addr nnpc;                      // next-next-cycle program counter
-                                        // used to implement branch delay slot
-                                        // not real register
-
       public:
-        void clear();
+        void clear()
+        {}
         void reset(std::string core_name, ThreadID num_threads,
-                   unsigned num_vpes, BaseCPU *_cpu);
+                   unsigned num_vpes, BaseCPU *_cpu)
+        {}
 
-        void setShadowSet(int css);
+        void setShadowSet(int css)
+        {}
 
       public:
-        Addr readPC();
-        void setPC(Addr val);
-
-        Addr readNextPC();
-        void setNextPC(Addr val);
-
-        Addr readNextNPC();
-        void setNextNPC(Addr val);
-
-        void serialize(EventManager *em, std::ostream &os);
+        void serialize(EventManager *em, std::ostream &os)
+        {}
         void unserialize(EventManager *em, Checkpoint *cp,
-            const std::string &section);
+            const std::string &section)
+        {}
 
     };
 
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 574deab6c..28ffc57aa 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -33,57 +33,7 @@
 #include "arch/sparc/miscregfile.hh"
 #include "cpu/thread_context.hh"
 
-class Checkpoint;
-
 using namespace SparcISA;
-using namespace std;
-
-//RegFile class methods
-Addr RegFile::readPC()
-{
-    return pc;
-}
-
-void RegFile::setPC(Addr val)
-{
-    pc = val;
-}
-
-Addr RegFile::readNextPC()
-{
-    return npc;
-}
-
-void RegFile::setNextPC(Addr val)
-{
-    npc = val;
-}
-
-Addr RegFile::readNextNPC()
-{
-    return nnpc;
-}
-
-void RegFile::setNextNPC(Addr val)
-{
-    nnpc = val;
-}
-
-void
-RegFile::serialize(EventManager *em, ostream &os)
-{
-    SERIALIZE_SCALAR(pc);
-    SERIALIZE_SCALAR(npc);
-    SERIALIZE_SCALAR(nnpc);
-}
-
-void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
-{
-    UNSERIALIZE_SCALAR(pc);
-    UNSERIALIZE_SCALAR(npc);
-    UNSERIALIZE_SCALAR(nnpc);
-}
 
 void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index b468d568b..b0c2aabbd 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -32,12 +32,11 @@
 #ifndef __ARCH_SPARC_REGFILE_HH__
 #define __ARCH_SPARC_REGFILE_HH__
 
+#include <iostream>
 #include <string>
 
 #include "arch/sparc/miscregfile.hh"
 #include "arch/sparc/sparc_traits.hh"
-#include "base/types.hh"
-#include "sim/serialize.hh"
 
 class Checkpoint;
 class EventManager;
@@ -50,31 +49,16 @@ namespace SparcISA
 
     class RegFile
     {
-      protected:
-        Addr pc;                // Program Counter
-        Addr npc;               // Next Program Counter
-        Addr nnpc;
-
-      public:
-        Addr readPC();
-        void setPC(Addr val);
-
-        Addr readNextPC();
-        void setNextPC(Addr val);
-
-        Addr readNextNPC();
-        void setNextNPC(Addr val);
-
       public:
 
         void clear()
         {}
 
-        void serialize(EventManager *em, std::ostream &os);
+        void serialize(EventManager *em, std::ostream &os)
+        {}
         void unserialize(EventManager *em, Checkpoint *cp,
-            const std::string &section);
-
-      public:
+            const std::string &section)
+        {}
     };
 
     void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 54bc0999d..67ef0b128 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -85,48 +85,11 @@
  * Authors: Gabe Black
  */
 
-#include "arch/x86/floatregs.hh"
 #include "arch/x86/miscregs.hh"
 #include "arch/x86/regfile.hh"
 #include "base/trace.hh"
-#include "sim/serialize.hh"
 #include "cpu/thread_context.hh"
 
-class Checkpoint;
-
-using namespace X86ISA;
-using namespace std;
-
-//RegFile class methods
-Addr RegFile::readPC()
-{
-    return rip;
-}
-
-void RegFile::setPC(Addr val)
-{
-    rip = val;
-}
-
-Addr RegFile::readNextPC()
-{
-    return nextRip;
-}
-
-void RegFile::setNextPC(Addr val)
-{
-    nextRip = val;
-}
-
-Addr RegFile::readNextNPC()
-{
-    //There's no way to know how big the -next- instruction will be.
-    return nextRip + 1;
-}
-
-void RegFile::setNextNPC(Addr val)
-{ }
-
 void
 X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index b832cbe28..6c0dc757e 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -58,14 +58,12 @@
 #ifndef __ARCH_X86_REGFILE_HH__
 #define __ARCH_X86_REGFILE_HH__
 
+#include <iostream>
 #include <string>
 
 #include "arch/x86/intregs.hh"
 #include "arch/x86/miscregs.hh"
-#include "arch/x86/isa_traits.hh"
 #include "arch/x86/x86_traits.hh"
-#include "arch/x86/types.hh"
-#include "base/types.hh"
 
 class Checkpoint;
 class EventManager;
@@ -88,28 +86,12 @@ namespace X86ISA
 
     class RegFile
     {
-      protected:
-        Addr rip; //Program Counter
-        Addr nextRip; //Next Program Counter
-
       public:
-        Addr readPC();
-        void setPC(Addr val);
-
-        Addr readNextPC();
-        void setNextPC(Addr val);
-
-        Addr readNextNPC();
-        void setNextNPC(Addr val);
-
-      public:
-
         void clear()
         {}
 
         void serialize(EventManager *em, std::ostream &os)
         {}
-
         void unserialize(EventManager *em, Checkpoint *cp,
                 const std::string &section)
         {}
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index d88e02ff1..2edaf8f55 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -63,8 +63,8 @@ using namespace std;
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            TheISA::TLB *_itb, TheISA::TLB *_dtb,
                            bool use_kernel_stats)
-    : ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
-      dtb(_dtb)
+    : ThreadState(_cpu, _thread_num),
+      cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
 
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
@@ -194,6 +194,11 @@ SimpleThread::serialize(ostream &os)
     regs.serialize(cpu, os);
     SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
     SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
+    SERIALIZE_SCALAR(microPC);
+    SERIALIZE_SCALAR(nextMicroPC);
+    SERIALIZE_SCALAR(PC);
+    SERIALIZE_SCALAR(nextPC);
+    SERIALIZE_SCALAR(nextNPC);
     // thread_num and cpu_id are deterministic from the config
 }
 
@@ -205,6 +210,11 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     regs.unserialize(cpu, cp, section);
     UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
     UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
+    UNSERIALIZE_SCALAR(microPC);
+    UNSERIALIZE_SCALAR(nextMicroPC);
+    UNSERIALIZE_SCALAR(PC);
+    UNSERIALIZE_SCALAR(nextPC);
+    UNSERIALIZE_SCALAR(nextNPC);
     // thread_num and cpu_id are deterministic from the config
 }
 
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 35a28dbb6..31e69bafe 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -107,6 +107,28 @@ class SimpleThread : public ThreadState
     TheISA::IntReg intRegs[TheISA::NumIntRegs];
     TheISA::ISA isa;    // one "instance" of the current ISA.
 
+    /** The current microcode pc for the currently executing macro
+     * operation.
+     */
+    MicroPC microPC;
+
+    /** The next microcode pc for the currently executing macro
+     * operation.
+     */
+    MicroPC nextMicroPC;
+
+    /** The current pc.
+     */
+    Addr PC;
+
+    /** The next pc.
+     */
+    Addr nextPC;
+
+    /** The next next pc.
+     */
+    Addr nextNPC;
+
   public:
     // pointer to CPU associated with this SimpleThread
     BaseCPU *cpu;
@@ -232,6 +254,9 @@ class SimpleThread : public ThreadState
     void clearArchRegs()
     {
         regs.clear();
+        microPC = 0;
+        nextMicroPC = 1;
+        PC = nextPC = nextNPC = 0;
         memset(intRegs, 0, sizeof(intRegs));
         memset(floatRegs.i, 0, sizeof(floatRegs.i));
     }
@@ -283,12 +308,12 @@ class SimpleThread : public ThreadState
 
     uint64_t readPC()
     {
-        return regs.readPC();
+        return PC;
     }
 
     void setPC(uint64_t val)
     {
-        regs.setPC(val);
+        PC = val;
     }
 
     uint64_t readMicroPC()
@@ -303,12 +328,12 @@ class SimpleThread : public ThreadState
 
     uint64_t readNextPC()
     {
-        return regs.readNextPC();
+        return nextPC;
     }
 
     void setNextPC(uint64_t val)
     {
-        regs.setNextPC(val);
+        nextPC = val;
     }
 
     uint64_t readNextMicroPC()
@@ -323,12 +348,18 @@ class SimpleThread : public ThreadState
 
     uint64_t readNextNPC()
     {
-        return regs.readNextNPC();
+#if ISA_HAS_DELAY_SLOT
+        return nextNPC;
+#else
+        return nextPC + sizeof(TheISA::MachInst);
+#endif
     }
 
     void setNextNPC(uint64_t val)
     {
-        regs.setNextNPC(val);
+#if ISA_HAS_DELAY_SLOT
+        nextNPC = val;
+#endif
     }
 
     MiscReg
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index d9d83fb00..53a56d9a6 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -56,7 +56,7 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid,
 #else
       port(NULL), process(_process), asid(_asid),
 #endif
-      microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
+      funcExeInst(0), storeCondFailures(0)
 {
 }
 
@@ -77,8 +77,6 @@ ThreadState::serialize(std::ostream &os)
     // thread_num and cpu_id are deterministic from the config
     SERIALIZE_SCALAR(funcExeInst);
     SERIALIZE_SCALAR(inst);
-    SERIALIZE_SCALAR(microPC);
-    SERIALIZE_SCALAR(nextMicroPC);
 
 #if FULL_SYSTEM
     Tick quiesceEndTick = 0;
@@ -98,8 +96,6 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
     // thread_num and cpu_id are deterministic from the config
     UNSERIALIZE_SCALAR(funcExeInst);
     UNSERIALIZE_SCALAR(inst);
-    UNSERIALIZE_SCALAR(microPC);
-    UNSERIALIZE_SCALAR(nextMicroPC);
 
 #if FULL_SYSTEM
     Tick quiesceEndTick;
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 525ecca86..ba61f431d 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -218,16 +218,6 @@ struct ThreadState {
      */
     TheISA::MachInst inst;
 
-    /** The current microcode pc for the currently executing macro
-     * operation.
-     */
-    MicroPC microPC;
-
-    /** The next microcode pc for the currently executing macro
-     * operation.
-     */
-    MicroPC nextMicroPC;
-
   public:
     /**
      * Temporary storage to pass the source address from copy_load to