diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:01 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:01 -0500 |
| commit | 4ebd44dc4f8d7b5085a8f1d1929cdd0381bc7c43 (patch) | |
| tree | 9e0b0c868735f864ec218963faa75cbbbf30047c | |
| parent | 386424ccb59ffdabcb4ce9d363903741e329ebcb (diff) | |
| download | gem5-4ebd44dc4f8d7b5085a8f1d1929cdd0381bc7c43.tar.xz | |
ARM: Flesh out the 32 bit thumb store single instructions.
| -rw-r--r-- | src/arch/arm/isa/bitfields.isa | 1 | ||||
| -rw-r--r-- | src/arch/arm/isa/thumbdecode.isa | 27 | ||||
| -rw-r--r-- | src/arch/arm/types.hh | 1 |
3 files changed, 28 insertions, 1 deletions
diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa index 1dcbddec3..5d191b6df 100644 --- a/src/arch/arm/isa/bitfields.isa +++ b/src/arch/arm/isa/bitfields.isa @@ -144,6 +144,7 @@ def bitfield HTOPCODE_8_7 htopcode8_7; def bitfield HTOPCODE_8_6 htopcode8_6; def bitfield HTOPCODE_8_5 htopcode8_5; def bitfield HTOPCODE_7 htopcode7; +def bitfield HTOPCODE_7_5 htopcode7_5; def bitfield HTOPCODE_6_5 htopcode6_5; def bitfield HTOPCODE_5_4 htopcode5_4; def bitfield HTOPCODE_4 htopcode4; diff --git a/src/arch/arm/isa/thumbdecode.isa b/src/arch/arm/isa/thumbdecode.isa index 9bf596b88..84a4d8267 100644 --- a/src/arch/arm/isa/thumbdecode.isa +++ b/src/arch/arm/isa/thumbdecode.isa @@ -388,7 +388,32 @@ 0x3: decode HTOPCODE_10_9 { 0x0: decode HTOPCODE_4 { 0x0: decode HTOPCODE_8 { - 0x0: WarnUnimpl::Store_single_data_item(); + 0x0: decode HTOPCODE_7_5 { + 0x0: decode LTOPCODE_11_8 { + 0x0: decode LTOPCODE_7_6 { + 0x0: WarnUnimpl::strb(); // register + } + 0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strb(); // immediate thumb + 0xe: WarnUnimpl::strbt(); + } + 0x1: decode LTOPCODE_11_8 { + 0x0: decode LTOPCODE_7_6 { + 0x0: WarnUnimpl::strh(); // register + } + 0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strh(); // immediate thumb + 0xe: WarnUnimpl::strht(); + } + 0x2: decode LTOPCODE_11_8 { + 0x0: decode LTOPCODE_7_6 { + 0x0: WarnUnimpl::str(); // register + } + 0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::str(); // immediate thumb + 0xe: WarnUnimpl::strt(); + } + 0x4: WarnUnimpl::strb(); // immediate, thumb + 0x5: WarnUnimpl::strh(); // immediate, thumb + 0x6: WarnUnimpl::str(); // immediate, thumb + } 0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store(); } 0x1: decode HTOPCODE_6_5 { diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 23152d3cf..9bdf69305 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -156,6 +156,7 @@ namespace ArmISA Bitfield<24, 22> htopcode8_6; Bitfield<24, 21> htopcode8_5; Bitfield<23> htopcode7; + Bitfield<23, 21> htopcode7_5; Bitfield<22, 21> htopcode6_5; Bitfield<21, 20> htopcode5_4; Bitfield<20> htopcode4; |