Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context

5 files changed, 4 insertions, 111 deletions

diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
index e05bfe2df..663115bb6 100644
--- a/src/arch/mips/regfile.cc
+++ b/src/arch/mips/regfile.cc
@@ -200,12 +200,6 @@ MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 }
 
 void
-MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest);
-{
-    panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
 MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
     panic("Copy Misc. Regs Not Implemented Yet\n");
diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
index c7edd1d76..dc5ff6f46 100644
--- a/src/cpu/inorder/SConscript
+++ b/src/cpu/inorder/SConscript
@@ -42,13 +42,12 @@ if 'InOrderCPU' in env['CPU_MODELS']:
 	TraceFlag('InOrderCPU')
 	TraceFlag('InOrderMDU')
 	TraceFlag('RegDepMap')
-	TraceFlag('Rename')
 	TraceFlag('InOrderDynInst')
 	TraceFlag('Resource')
 	TraceFlag('RefCount')
 
 	CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
-	       'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
+	       'InOrderMDU', 'RegDepMap', 'Resource'])
 
 	Source('pipeline_traits.cc')        
 	Source('inorder_dyn_inst.cc')
@@ -74,8 +73,6 @@ if 'InOrderCPU' in env['CPU_MODELS']:
 	Source('../o3/btb.cc')
 	Source('../o3/tournament_pred.cc')
 	Source('../o3/2bit_local_pred.cc')
-	Source('../o3/free_list.cc')
-	Source('../o3/rename_map.cc')
 	Source('../o3/ras.cc')
 	Source('thread_context.cc')
 	Source('cpu.cc')
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 34eabbad4..6c1cdc9dc 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -77,7 +77,6 @@ class InOrderCPU : public BaseCPU
     typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::MiscReg MiscReg;
     typedef TheISA::RegFile RegFile;
-    typedef SimpleRenameMap RenameMap;
 
     //DynInstPtr TypeDefs
     typedef ThePipeline::DynInstPtr DynInstPtr;
@@ -586,14 +585,6 @@ class InOrderCPU : public BaseCPU
 
     std::list<unsigned> fetchPriorityList;
 
-     /** Rename Map for architectural-to-physical register mappings.
-      *  In a In-order processor, the mapping is fixed
-      *  (e.g. Thread 1: 0-31, Thread 1: 32-63, etc.)
-      *  In a Out-of-Order processor, this is used to maintain
-      *  sequential consistency (?right word here?).
-      */
-     RenameMap renameMap[ThePipeline::MaxThreads];
-
   protected:
     /** Active Threads List */
     std::list<unsigned> activeThreads;
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index 5e2c789cb..2470ee676 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -44,7 +44,6 @@ InOrderThreadContext::takeOverFrom(ThreadContext *old_context)
     // copy over functional state
     setStatus(old_context->status());
     copyArchRegs(old_context);
-    //setCpuId(0/*old_context->readCpuId()*/);
 
     thread->funcExeInst = old_context->readFuncExeInst();
     old_context->setStatus(ThreadContext::Unallocated);
@@ -61,18 +60,8 @@ InOrderThreadContext::activate(int delay)
     if (thread->status() == ThreadContext::Active)
         return;
 
-    // @TODO: Make this process useful again...
-    //if (thread->status() == ThreadContext::Unallocated) {
-        // Allows the CPU to drain partitioned resources
-        // before inserting thread into the CPU
-        // (e.g. bind physical registers)
-        //cpu->activateWhenReady(thread->readTid());
-        //return;
-    //}
-
     thread->setStatus(ThreadContext::Active);
 
-    // status() == Suspended
     cpu->activateContext(thread->readTid(), delay);
 }
 
@@ -157,37 +146,9 @@ InOrderThreadContext:: getInst()
 
 
 void
-InOrderThreadContext::copyArchRegs(ThreadContext *tc)
+InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
 {
-    unsigned tid = thread->readTid();
-    PhysRegIndex renamed_reg;
-
-    // First loop through the integer registers.
-    for (int i = 0; i < TheISA::NumIntRegs; ++i) {
-        renamed_reg = cpu->renameMap[tid].lookup(i);
-
-        DPRINTF(InOrderCPU, "Copying over register %i, had data %lli, "
-                "now has data %lli.\n",
-                renamed_reg, cpu->readIntReg(renamed_reg, tid),
-                tc->readIntReg(i));
-
-        cpu->setIntReg(renamed_reg, tc->readIntReg(i), tid);
-    }
-
-    // Then loop through the floating point registers.
-    for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
-        renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
-        cpu->setFloatRegBits(renamed_reg, tc->readFloatRegBits(i), tid);
-    }
-
-    // Copy the misc regs.
-    TheISA::copyMiscRegs(tc, this);
-
-    // Then finally set the PC and the next PC.
-    cpu->setPC(tc->readPC(), tid);
-    cpu->setNextPC(tc->readNextPC(), tid);
-    cpu->setNextNPC(tc->readNextNPC(), tid);
-    this->thread->funcExeInst = tc->readFuncExeInst();
+    TheISA::copyRegs(src_tc, this);
 }
 
 
@@ -236,33 +197,18 @@ void
 InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
 {
     cpu->setIntReg(reg_idx, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //  cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
 InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val, int width)
 {
     cpu->setFloatReg(reg_idx, val, thread->readTid(), width);
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
 InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
 {
     cpu->setFloatReg(reg_idx, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
@@ -270,22 +216,12 @@ InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val,
                                     int width)
 {
     cpu->setFloatRegBits(reg_idx, val, thread->readTid(), width);
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
 InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     cpu->setFloatRegBits(reg_idx, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
@@ -299,11 +235,6 @@ InOrderThreadContext::setPC(uint64_t val)
 {
     DPRINTF(InOrderCPU, "Setting PC to %08p\n", val);
     cpu->setPC(val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
@@ -311,11 +242,6 @@ InOrderThreadContext::setNextPC(uint64_t val)
 {
     DPRINTF(InOrderCPU, "Setting NPC to %08p\n", val);
     cpu->setNextPC(val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
@@ -323,33 +249,18 @@ InOrderThreadContext::setNextNPC(uint64_t val)
 {
     DPRINTF(InOrderCPU, "Setting NNPC to %08p\n", val);
     cpu->setNextNPC(val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
 InOrderThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 {
     cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 void
 InOrderThreadContext::setMiscReg(int misc_reg, const MiscReg &val)
 {
     cpu->setMiscReg(misc_reg, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    //if (!thread->trapPending && !thread->inSyscall) {
-    //cpu->squashFromTC(thread->readTid());
-    //}
 }
 
 TheISA::IntReg
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 919d5d2b6..708dcf6b3 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -147,7 +147,7 @@ class InOrderThreadContext : public ThreadContext
     virtual TheISA::MachInst getInst();
 
     /** Copies the architectural registers from another TC into this TC. */
-    virtual void copyArchRegs(ThreadContext *tc);
+    virtual void copyArchRegs(ThreadContext *src_tc);
 
     /** Resets all architectural registers to 0. */
     virtual void clearArchRegs();