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| author | Ali Saidi <ali.saidi@arm.com> | 2014-03-07 15:56:23 -0500 |
|---|---|---|
| committer | Ali Saidi <ali.saidi@arm.com> | 2014-03-07 15:56:23 -0500 |
| commit | bf39a475fe8c796e5b0f5b37ee2e4aca724d05f3 (patch) | |
| tree | a0a877c2ef712e0b1341834f887ee3320542f8cf | |
| parent | f4a897d8e3e7a9fe5f409c0f15dfa5ba9438776c (diff) | |
| download | gem5-bf39a475fe8c796e5b0f5b37ee2e4aca724d05f3.tar.xz | |
mem: Wakeup sleeping CPUs without caches on LLSC
For systems without caches, the LLSC code does not get snoops for
wake-ups. We add the LLSC code in the abstract memory to do the job
for us.
| -rw-r--r-- | src/arch/null/cpu_dummy.hh | 1 | ||||
| -rw-r--r-- | src/mem/abstract_mem.cc | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh index ed6f6d1d6..f546b4141 100644 --- a/src/arch/null/cpu_dummy.hh +++ b/src/arch/null/cpu_dummy.hh @@ -47,6 +47,7 @@ class BaseCPU public: static int numSimulatedInsts() { return 0; } static int numSimulatedOps() { return 0; } + static void wakeup() { ; } }; #endif // __ARCH_NULL_CPU_DUMMY_HH__ diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc index a169243e9..98f03b9af 100644 --- a/src/mem/abstract_mem.cc +++ b/src/mem/abstract_mem.cc @@ -44,6 +44,8 @@ #include "arch/registers.hh" #include "config/the_isa.hh" +#include "cpu/base.hh" +#include "cpu/thread_context.hh" #include "debug/LLSC.hh" #include "debug/MemoryAccess.hh" #include "mem/abstract_mem.hh" @@ -260,6 +262,12 @@ AbstractMemory::checkLockedAddrList(PacketPtr pkt) if (i->addr == paddr) { DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n", i->contextId, paddr); + // For ARM, a spinlock would typically include a Wait + // For Event (WFE) to conserve energy. The ARMv8 + // architecture specifies that an event is + // automatically generated when clearing the exclusive + // monitor to wake up the processor in WFE. + system()->getThreadContext(i->contextId)->getCpuPtr()->wakeup(); i = lockedAddrList.erase(i); } else { i++; |