diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-07-21 15:46:12 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-07-21 15:46:12 -0400 |
commit | bf90e1dbde78906b2d2831c123166ce19cf0ec53 (patch) | |
tree | eb8c710612dad8a28c805131084a6fe0253c2dd1 | |
parent | bd33d8d4ac43569f0c163b35aae13d2677faa875 (diff) | |
download | gem5-bf90e1dbde78906b2d2831c123166ce19cf0ec53.tar.xz |
Minor functionality updates.
SConstruct:
Include an option to specify the CPUs being tested.
src/cpu/SConscript:
Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker.
src/python/m5/objects/O3CPU.py:
Include default options. Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used.
tests/SConscript:
Several minor updates (sorry for one commit). Updated the copyright and fixed some m5 style issues. Also added the ability to specify which CPUs to run the tests on.
--HG--
extra : convert_revision : b0b801115705544ea02e572e31314f7bb8b5f0f2
-rw-r--r-- | SConstruct | 2 | ||||
-rw-r--r-- | src/cpu/SConscript | 3 | ||||
-rw-r--r-- | src/python/m5/objects/O3CPU.py | 144 | ||||
-rw-r--r-- | tests/SConscript | 38 |
4 files changed, 109 insertions, 78 deletions
diff --git a/SConstruct b/SConstruct index 259b6c583..ce80068f3 100644 --- a/SConstruct +++ b/SConstruct @@ -279,6 +279,8 @@ sticky_opts.AddOptions( # scons 0.96.90 or later. ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU', env['ALL_CPU_LIST']), + ListOption('TEST_CPU_MODELS', 'CPU models to test if regression is being run', '', + env['ALL_CPU_LIST']), BoolOption('ALPHA_TLASER', 'Model Alpha TurboLaser platform (vs. Tsunami)', False), BoolOption('NO_FAST_ALLOC', 'Disable fast object allocator', False), diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 7d45c7870..2bb9a2399 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -160,7 +160,8 @@ if 'O3CPU' in env['CPU_MODELS']: ''') if env['USE_CHECKER']: sources += Split('o3/checker_builder.cc') - env['SMT_CPU_MODELS'].append('O3CPU') + else: + env['SMT_CPU_MODELS'].append('O3CPU') # Checker doesn't support SMT right now if 'OzoneCPU' in env['CPU_MODELS']: need_bp_unit = True diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index d6bc454ad..41208929a 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -1,91 +1,101 @@ from m5 import build_env from m5.config import * from BaseCPU import BaseCPU +from Checker import O3Checker class DerivO3CPU(BaseCPU): type = 'DerivO3CPU' - activity = Param.Unsigned("Initial count") - numThreads = Param.Unsigned("number of HW thread contexts") - - checker = Param.BaseCPU(NULL, "checker") + activity = Param.Unsigned(0, "Initial count") + numThreads = Param.Unsigned(1, "number of HW thread contexts") + + if build_env['USE_CHECKER']: + if not build_env['FULL_SYSTEM']: + checker = Param.BaseCPU(O3Checker(workload=Parent.workload, + exitOnError=True, + warnOnlyOnLoadError=False), + "checker") + else: + checker = Param.BaseCPU(O3Checker(exitOnError=True, warnOnlyOnLoadError=False), "checker") + checker.itb = Parent.itb + checker.dtb = Parent.dtb cachePorts = Param.Unsigned("Cache Ports") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") - renameToFetchDelay = Param.Unsigned("Rename to fetch delay") - iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned("Commit to fetch delay") - fetchWidth = Param.Unsigned("Fetch width") + decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") + renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") + iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") + fetchWidth = Param.Unsigned(8, "Fetch width") - renameToDecodeDelay = Param.Unsigned("Rename to decode delay") - iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " + renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") + iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " "delay") - commitToDecodeDelay = Param.Unsigned("Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") - decodeWidth = Param.Unsigned("Decode width") + commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") + fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") + decodeWidth = Param.Unsigned(8, "Decode width") - iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " + iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " "delay") - commitToRenameDelay = Param.Unsigned("Commit to rename delay") - decodeToRenameDelay = Param.Unsigned("Decode to rename delay") - renameWidth = Param.Unsigned("Rename width") + commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") + decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") + renameWidth = Param.Unsigned(8, "Rename width") - commitToIEWDelay = Param.Unsigned("Commit to " + commitToIEWDelay = Param.Unsigned(1, "Commit to " "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned("Rename to " + renameToIEWDelay = Param.Unsigned(2, "Rename to " "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " + issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " "to the IEW stage)") - dispatchWidth = Param.Unsigned("Dispatch width") - issueWidth = Param.Unsigned("Issue width") - wbWidth = Param.Unsigned("Writeback width") - wbDepth = Param.Unsigned("Writeback depth") - fuPool = Param.FUPool(NULL, "Functional Unit pool") + dispatchWidth = Param.Unsigned(8, "Dispatch width") + issueWidth = Param.Unsigned(8, "Issue width") + wbWidth = Param.Unsigned(8, "Writeback width") + wbDepth = Param.Unsigned(1, "Writeback depth") + fuPool = Param.FUPool("Functional Unit pool") - iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " + iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " "delay") - renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") - commitWidth = Param.Unsigned("Commit width") - squashWidth = Param.Unsigned("Squash width") - trapLatency = Param.Tick("Trap latency") - fetchTrapLatency = Param.Tick("Fetch trap latency") - - backComSize = Param.Unsigned("Time buffer size for backwards communication") - forwardComSize = Param.Unsigned("Time buffer size for forward communication") - - predType = Param.String("Branch predictor type ('local', 'tournament')") - localPredictorSize = Param.Unsigned("Size of local predictor") - localCtrBits = Param.Unsigned("Bits per counter") - localHistoryTableSize = Param.Unsigned("Size of local history table") - localHistoryBits = Param.Unsigned("Bits for the local history") - globalPredictorSize = Param.Unsigned("Size of global predictor") - globalCtrBits = Param.Unsigned("Bits per counter") - globalHistoryBits = Param.Unsigned("Bits of history") - choicePredictorSize = Param.Unsigned("Size of choice predictor") - choiceCtrBits = Param.Unsigned("Bits of choice counters") - - BTBEntries = Param.Unsigned("Number of BTB entries") - BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") - - RASSize = Param.Unsigned("RAS size") - - LQEntries = Param.Unsigned("Number of load queue entries") - SQEntries = Param.Unsigned("Number of store queue entries") - LFSTSize = Param.Unsigned("Last fetched store table size") - SSITSize = Param.Unsigned("Store set ID table size") - - numRobs = Param.Unsigned("Number of Reorder Buffers"); - - numPhysIntRegs = Param.Unsigned("Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned("Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned("Number of instruction queue entries") - numROBEntries = Param.Unsigned("Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") + renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") + commitWidth = Param.Unsigned(8, "Commit width") + squashWidth = Param.Unsigned(8, "Squash width") + trapLatency = Param.Tick(13, "Trap latency") + fetchTrapLatency = Param.Tick(1, "Fetch trap latency") + + backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") + forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") + + predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") + localPredictorSize = Param.Unsigned(2048, "Size of local predictor") + localCtrBits = Param.Unsigned(2, "Bits per counter") + localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") + localHistoryBits = Param.Unsigned(11, "Bits for the local history") + globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") + globalCtrBits = Param.Unsigned(2, "Bits per counter") + globalHistoryBits = Param.Unsigned(4096, "Bits of history") + choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") + choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") + + BTBEntries = Param.Unsigned(4096, "Number of BTB entries") + BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") + + RASSize = Param.Unsigned(16, "RAS size") + + LQEntries = Param.Unsigned(32, "Number of load queue entries") + SQEntries = Param.Unsigned(32, "Number of store queue entries") + LFSTSize = Param.Unsigned(1024, "Last fetched store table size") + SSITSize = Param.Unsigned(1024, "Store set ID table size") + + numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); + + numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") + numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " + "registers") + numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") + numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") + + instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/tests/SConscript b/tests/SConscript index 5eadce6d4..8e4d1da01 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -1,6 +1,6 @@ # -*- mode:python -*- -# Copyright (c) 2004-2005 The Regents of The University of Michigan +# Copyright (c) 2004-2006 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -25,6 +25,9 @@ # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt +# Kevin Lim import os import sys @@ -136,7 +139,8 @@ def update_test_string(target, source, env): updateAction = env.Action(update_test, update_test_string) -def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=15): +def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', + timeout=15): """Define a test. Args: @@ -153,12 +157,23 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1 default_refdir = True if len(cpu_list) == 0: cpu_list = env['CPU_MODELS'] + if env['TEST_CPU_MODELS']: + temp_cpu_list = [] + for i in env['TEST_CPU_MODELS']: + if i in cpu_list: + temp_cpu_list.append(i) + cpu_list = temp_cpu_list +# Code commented out that shows the general structure if we want to test +# different OS's as well. # if len(os_list) == 0: -# raise RuntimeError, "No OS specified" +# for test_cpu in cpu_list: +# build_cpu_test(env, category, '', test_cpu, refdir, timeout) # else: # for test_os in os_list: -# build_cpu_test(env, category, test_os, cpu_list, refdir, timeout) - # Loop through CPU models and generate proper options, ref directories for each +# for test_cpu in cpu_list: +# build_cpu_test(env, category, test_os, test_cpu, refdir, +# timeout) + # Loop through CPU models and generate proper options, ref directories for cpu in cpu_list: test_os = '' if cpu == "AtomicSimpleCPU": @@ -171,7 +186,8 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1 raise TypeError, "Unknown CPU model specified" if default_refdir: - # Reference stats located in ref/arch/os/cpu or ref/arch/cpu if no OS specified + # Reference stats located in ref/arch/os/cpu or ref/arch/cpu + # if no OS specified test_refdir = os.path.join(refdir, env['TARGET_ISA']) if test_os != '': test_refdir = os.path.join(test_refdir, test_os) @@ -202,8 +218,8 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1 else: cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr] - env.Command([stdout_string, stderr_string, m5stats_string], [env.M5Binary, 'run.py'], - ' '.join(cmd)) + env.Command([stdout_string, stderr_string, m5stats_string], + [env.M5Binary, 'run.py'], ' '.join(cmd)) # order of targets is important... see check_test env.Command([outdiff_string, statsdiff_string, status_string], @@ -212,10 +228,12 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1 # phony target to echo status if env['update_ref']: - p = env.Command(cpu_option[1] + '_update', [ref_stats, m5stats_string, status_string], + p = env.Command(cpu_option[1] + '_update', + [ref_stats, m5stats_string, status_string], updateAction) else: - p = env.Command(cpu_option[1] + '_print', [status_string], printAction) + p = env.Command(cpu_option[1] + '_print', [status_string], + printAction) env.AlwaysBuild(p) env.Tests.setdefault(category, []) |