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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-31 22:21:01 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-31 22:21:01 -0800 |
| commit | deb97742c7ada2008ec79aaf1791f7db3c6a2b06 (patch) | |
| tree | cc3e2f2237aa3c505a0af238f5624e5ee3d80c33 | |
| parent | ab2f864af2fd38cbf141708550409f3ca72c675f (diff) | |
| download | gem5-deb97742c7ada2008ec79aaf1791f7db3c6a2b06.tar.xz | |
m5: Added PROTOCOL default for regress fix
| -rw-r--r-- | build_opts/ALPHA_FS | 1 | ||||
| -rw-r--r-- | build_opts/ALPHA_SE | 1 | ||||
| -rw-r--r-- | build_opts/ARM_FS | 1 | ||||
| -rw-r--r-- | build_opts/ARM_SE | 1 | ||||
| -rw-r--r-- | build_opts/MIPS_FS | 1 | ||||
| -rw-r--r-- | build_opts/MIPS_SE | 3 | ||||
| -rw-r--r-- | build_opts/POWER_SE | 1 | ||||
| -rw-r--r-- | build_opts/SPARC_FS | 1 | ||||
| -rw-r--r-- | build_opts/SPARC_SE | 1 | ||||
| -rw-r--r-- | build_opts/X86_FS | 1 | ||||
| -rw-r--r-- | build_opts/X86_SE | 1 |
11 files changed, 12 insertions, 1 deletions
diff --git a/build_opts/ALPHA_FS b/build_opts/ALPHA_FS index e69cff04b..3908039d1 100644 --- a/build_opts/ALPHA_FS +++ b/build_opts/ALPHA_FS @@ -1,3 +1,4 @@ TARGET_ISA = 'alpha' FULL_SYSTEM = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/ALPHA_SE b/build_opts/ALPHA_SE index dcd8559fc..b21fec4cb 100644 --- a/build_opts/ALPHA_SE +++ b/build_opts/ALPHA_SE @@ -1,3 +1,4 @@ FULL_SYSTEM = 0 SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/ARM_FS b/build_opts/ARM_FS index 508bad76e..9d518142d 100644 --- a/build_opts/ARM_FS +++ b/build_opts/ARM_FS @@ -1,3 +1,4 @@ TARGET_ISA = 'arm' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff --git a/build_opts/ARM_SE b/build_opts/ARM_SE index 93770ac80..5019edb0a 100644 --- a/build_opts/ARM_SE +++ b/build_opts/ARM_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'arm' FULL_SYSTEM = 0 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/MIPS_FS b/build_opts/MIPS_FS index 81d7fd7a1..3e08a2fcd 100644 --- a/build_opts/MIPS_FS +++ b/build_opts/MIPS_FS @@ -1,2 +1,3 @@ TARGET_ISA = 'mips' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff --git a/build_opts/MIPS_SE b/build_opts/MIPS_SE index d3e449f42..085557898 100644 --- a/build_opts/MIPS_SE +++ b/build_opts/MIPS_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'mips' FULL_SYSTEM = 0 -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
\ No newline at end of file +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/POWER_SE b/build_opts/POWER_SE index d76ca7180..13e175ebc 100644 --- a/build_opts/POWER_SE +++ b/build_opts/POWER_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'power' FULL_SYSTEM = 0 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/SPARC_FS b/build_opts/SPARC_FS index 7c8bda0ce..f1dd81481 100644 --- a/build_opts/SPARC_FS +++ b/build_opts/SPARC_FS @@ -1,3 +1,4 @@ TARGET_ISA = 'sparc' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff --git a/build_opts/SPARC_SE b/build_opts/SPARC_SE index b288d3908..802176bd0 100644 --- a/build_opts/SPARC_SE +++ b/build_opts/SPARC_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'sparc' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' FULL_SYSTEM = 0 +PROTOCOL = 'MI_example' diff --git a/build_opts/X86_FS b/build_opts/X86_FS index 7cc6847f2..72cba7443 100644 --- a/build_opts/X86_FS +++ b/build_opts/X86_FS @@ -1,3 +1,4 @@ TARGET_ISA = 'x86' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff --git a/build_opts/X86_SE b/build_opts/X86_SE index 5913cde1e..3e372726d 100644 --- a/build_opts/X86_SE +++ b/build_opts/X86_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'x86' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 0 +PROTOCOL = 'MI_example' |